17 #include <soc/bootblock.h>
19 #include <soc/pci_devs.h>
117 const char cpu_not_found[] =
"Platform info not available";
118 const char *cpu_name = cpu_not_found;
120 static const char *
const mode[] = {
"NOT ",
""};
125 cpuidr =
cpuid(index);
126 if (cpuidr.
eax >= 0x80000004) {
129 for (i = 2; i <= 4; i++) {
130 cpuidr =
cpuid(index + i);
137 cpu_name = (
char *)p;
140 while (cpu_name[0] ==
' ' &&
strlen(cpu_name) > 0)
159 aes = (cpu_feature_flag &
CPUID_AES) ? 1 : 0;
160 txt = (cpu_feature_flag &
CPUID_SMX) ? 1 : 0;
161 vt = (cpu_feature_flag &
CPUID_VMX) ? 1 : 0;
163 "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
164 mode[aes], mode[txt], mode[vt]);
173 const char *mch_type =
"Unknown";
183 mchid, mch_revision, mch_type);
208 const char *igd_type =
"Unknown";
#define printk(level,...)
uint32_t cpu_get_feature_flags_ecx(void)
uint32_t cpu_get_cpuid(void)
#define CPUID_TIGERLAKE_B0
#define CPUID_TIGERLAKE_A0
#define CPUID_TIGERLAKE_R0
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
uint32_t get_current_microcode_rev(void)
#define PCI_DID_INTEL_TGP_ESPI_10
#define PCI_DID_INTEL_TGP_ESPI_16
#define PCI_DID_INTEL_TGP_ESPI_9
#define PCI_DID_INTEL_TGL_ID_H_6_1
#define PCI_DID_INTEL_TGP_ESPI_14
#define PCI_DID_INTEL_TGP_ESPI_17
#define PCI_DID_INTEL_TGP_ESPI_6
#define PCI_DID_INTEL_TGP_SUPER_U_ESPI
#define PCI_DID_INTEL_TGP_ESPI_22
#define PCI_DID_INTEL_TGL_GT0
#define PCI_DID_INTEL_TGP_H_ESPI_H570
#define PCI_DID_INTEL_TGL_ID_U_4_2
#define PCI_DID_INTEL_TGP_ESPI_20
#define PCI_DID_INTEL_TGP_ESPI_7
#define PCI_DID_INTEL_TGP_ESPI_15
#define PCI_DID_INTEL_TGL_GT3_ULT
#define PCI_DID_INTEL_TGP_H_ESPI_QM580
#define PCI_DID_INTEL_TGP_ESPI_3
#define PCI_DID_INTEL_TGP_ESPI_24
#define PCI_DID_INTEL_TGL_ID_Y_4_2
#define PCI_DID_INTEL_TGP_BASE_U_ESPI
#define PCI_DID_INTEL_TGP_H_ESPI_HM570
#define PCI_DID_INTEL_TGP_ESPI_26
#define PCI_DID_INTEL_TGP_ESPI_2
#define PCI_DID_INTEL_TGL_GT2_ULT_1
#define PCI_DID_INTEL_TGP_H_ESPI_Z590
#define PCI_DID_INTEL_TGP_PREMIUM_Y_ESPI
#define PCI_DID_INTEL_TGP_H_ESPI_Q570
#define PCI_DID_INTEL_TGL_GT1_H_16
#define PCI_DID_INTEL_TGL_GT1_H_32
#define PCI_DID_INTEL_TGP_H_ESPI_H510
#define PCI_DID_INTEL_TGL_ID_Y_2_2
#define PCI_DID_INTEL_TGL_GT2_ULX
#define PCI_DID_INTEL_TGP_ESPI_8
#define PCI_DID_INTEL_TGP_ESPI_25
#define PCI_DID_INTEL_TGP_ESPI_11
#define PCI_DID_INTEL_TGP_PREMIUM_U_ESPI
#define PCI_DID_INTEL_TGP_ESPI_0
#define PCI_DID_INTEL_TGP_ESPI_12
#define PCI_DID_INTEL_TGP_ESPI_18
#define PCI_DID_INTEL_TGP_ESPI_13
#define PCI_DID_INTEL_TGP_H_ESPI_WM590
#define PCI_DID_INTEL_TGP_ESPI_4
#define PCI_DID_INTEL_TGP_H_ESPI_B560
#define PCI_DID_INTEL_TGP_ESPI_19
#define PCI_DID_INTEL_TGL_ID_U_2_2
#define PCI_DID_INTEL_TGP_SUPER_Y_ESPI
#define PCI_DID_INTEL_TGP_ESPI_21
#define PCI_DID_INTEL_TGP_H_ESPI_W580
#define PCI_DID_INTEL_TGL_ID_H_8_1
#define PCI_DID_INTEL_TGL_GT2_ULT
#define PCI_DID_INTEL_TGP_ESPI_1
#define PCI_DID_INTEL_TGP_ESPI_23
#define PCI_DID_INTEL_TGP_ESPI_5
size_t strlen(const char *src)