coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
report_platform.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /*
4  * This file is created based on Intel Tiger Lake Platform Stepping and IDs
5  * Document number: 605534
6  * Chapter number: 2, 4, 5, 6
7  */
8 
9 #include <arch/cpu.h>
10 #include <device/pci_ops.h>
11 #include <console/console.h>
12 #include <cpu/intel/cpu_ids.h>
13 #include <cpu/intel/microcode.h>
14 #include <cpu/x86/msr.h>
15 #include <device/pci.h>
16 #include <device/pci_ids.h>
17 #include <soc/bootblock.h>
18 #include <soc/pch.h>
19 #include <soc/pci_devs.h>
20 #include <string.h>
21 
22 static struct {
24  const char *name;
25 } cpu_table[] = {
26  { CPUID_TIGERLAKE_A0, "Tigerlake A0" },
27  { CPUID_TIGERLAKE_B0, "Tigerlake B0" },
28  { CPUID_TIGERLAKE_R0, "Tigerlake R0" },
29 };
30 
31 static struct {
33  const char *name;
34 } mch_table[] = {
35  { PCI_DID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" },
36  { PCI_DID_INTEL_TGL_ID_U_4_2, "Tigerlake-U-4-2" },
37  { PCI_DID_INTEL_TGL_ID_Y_2_2, "Tigerlake-Y-2-2" },
38  { PCI_DID_INTEL_TGL_ID_Y_4_2, "Tigerlake-Y-4-2" },
39  { PCI_DID_INTEL_TGL_ID_H_6_1, "Tigerlake-H-6-1" },
40  { PCI_DID_INTEL_TGL_ID_H_8_1, "Tigerlake-H-8-1" },
41 };
42 
43 static struct {
45  const char *name;
46 } pch_table[] = {
47  { PCI_DID_INTEL_TGP_ESPI_0, "Tigerlake-Base SKU" },
48  { PCI_DID_INTEL_TGP_SUPER_U_ESPI, "Tigerlake-U Super SKU" },
49  { PCI_DID_INTEL_TGP_PREMIUM_U_ESPI, "Tigerlake-U Premium SKU" },
50  { PCI_DID_INTEL_TGP_BASE_U_ESPI, "Tigerlake-U Base SKU" },
51  { PCI_DID_INTEL_TGP_ESPI_1, "Tigerlake-Base SKU" },
52  { PCI_DID_INTEL_TGP_ESPI_2, "Tigerlake-Base SKU" },
53  { PCI_DID_INTEL_TGP_SUPER_Y_ESPI, "Tigerlake-Y Super SKU" },
54  { PCI_DID_INTEL_TGP_PREMIUM_Y_ESPI, "Tigerlake-Y Premium SKU" },
55  { PCI_DID_INTEL_TGP_ESPI_3, "Tigerlake-Base SKU" },
56  { PCI_DID_INTEL_TGP_ESPI_4, "Tigerlake-Base SKU" },
57  { PCI_DID_INTEL_TGP_ESPI_5, "Tigerlake-Base SKU" },
58  { PCI_DID_INTEL_TGP_ESPI_6, "Tigerlake-Base SKU" },
59  { PCI_DID_INTEL_TGP_ESPI_7, "Tigerlake-Base SKU" },
60  { PCI_DID_INTEL_TGP_ESPI_8, "Tigerlake-Base SKU" },
61  { PCI_DID_INTEL_TGP_ESPI_9, "Tigerlake-Base SKU" },
62  { PCI_DID_INTEL_TGP_ESPI_10, "Tigerlake-Base SKU" },
63  { PCI_DID_INTEL_TGP_ESPI_11, "Tigerlake-Base SKU" },
64  { PCI_DID_INTEL_TGP_ESPI_12, "Tigerlake-Base SKU" },
65  { PCI_DID_INTEL_TGP_ESPI_13, "Tigerlake-Base SKU" },
66  { PCI_DID_INTEL_TGP_ESPI_14, "Tigerlake-Base SKU" },
67  { PCI_DID_INTEL_TGP_ESPI_15, "Tigerlake-Base SKU" },
68  { PCI_DID_INTEL_TGP_ESPI_16, "Tigerlake-Base SKU" },
69  { PCI_DID_INTEL_TGP_ESPI_17, "Tigerlake-Base SKU" },
70  { PCI_DID_INTEL_TGP_ESPI_18, "Tigerlake-Base SKU" },
71  { PCI_DID_INTEL_TGP_ESPI_19, "Tigerlake-Base SKU" },
72  { PCI_DID_INTEL_TGP_ESPI_20, "Tigerlake-Base SKU" },
73  { PCI_DID_INTEL_TGP_ESPI_21, "Tigerlake-Base SKU" },
74  { PCI_DID_INTEL_TGP_ESPI_22, "Tigerlake-Base SKU" },
75  { PCI_DID_INTEL_TGP_ESPI_23, "Tigerlake-Base SKU" },
76  { PCI_DID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" },
77  { PCI_DID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" },
78  { PCI_DID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" },
79  { PCI_DID_INTEL_TGP_H_ESPI_B560, "Tigerlake-H B560" },
80  { PCI_DID_INTEL_TGP_H_ESPI_H510, "Tigerlake-H H510" },
81  { PCI_DID_INTEL_TGP_H_ESPI_H570, "Tigerlake-H H570" },
82  { PCI_DID_INTEL_TGP_H_ESPI_Q570, "Tigerlake-H Q570" },
83  { PCI_DID_INTEL_TGP_H_ESPI_W580, "Tigerlake-H W580" },
84  { PCI_DID_INTEL_TGP_H_ESPI_Z590, "Tigerlake-H Z590" },
85  { PCI_DID_INTEL_TGP_H_ESPI_HM570, "Tigerlake-H HM570" },
86  { PCI_DID_INTEL_TGP_H_ESPI_QM580, "Tigerlake-H QM580" },
87  { PCI_DID_INTEL_TGP_H_ESPI_WM590, "Tigerlake-H WM590" },
88 };
89 
90 static struct {
92  const char *name;
93 } igd_table[] = {
94  { PCI_DID_INTEL_TGL_GT0, "Tigerlake U GT0" },
95  { PCI_DID_INTEL_TGL_GT1_H_32, "Tigerlake H GT1 32EU" },
96  { PCI_DID_INTEL_TGL_GT1_H_16, "Tigerlake H GT1 16EU" },
97  { PCI_DID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" },
98  { PCI_DID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" },
99  { PCI_DID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" },
100  { PCI_DID_INTEL_TGL_GT2_ULT_1, "Tigerlake U GT2 1" },
101 };
102 
104 {
105  return pci_read_config8(dev, PCI_REVISION_ID);
106 }
107 
108 static inline uint16_t get_dev_id(pci_devfn_t dev)
109 {
110  return pci_read_config16(dev, PCI_DEVICE_ID);
111 }
112 
113 static void report_cpu_info(void)
114 {
115  struct cpuid_result cpuidr;
116  u32 i, index, cpu_id, cpu_feature_flag;
117  const char cpu_not_found[] = "Platform info not available";
118  const char *cpu_name = cpu_not_found; /* 48 bytes are reported */
119  int vt, txt, aes;
120  static const char *const mode[] = {"NOT ", ""};
121  const char *cpu_type = "Unknown";
122  u32 p[13];
123 
124  index = 0x80000000;
125  cpuidr = cpuid(index);
126  if (cpuidr.eax >= 0x80000004) {
127  int j = 0;
128 
129  for (i = 2; i <= 4; i++) {
130  cpuidr = cpuid(index + i);
131  p[j++] = cpuidr.eax;
132  p[j++] = cpuidr.ebx;
133  p[j++] = cpuidr.ecx;
134  p[j++] = cpuidr.edx;
135  }
136  p[12] = 0;
137  cpu_name = (char *)p;
138 
139  /* Skip leading spaces in CPU name string */
140  while (cpu_name[0] == ' ' && strlen(cpu_name) > 0)
141  cpu_name++;
142  }
143 
144  cpu_id = cpu_get_cpuid();
145 
146  /* Look for string to match the name */
147  for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
148  if (cpu_table[i].cpuid == cpu_id) {
149  cpu_type = cpu_table[i].name;
150  break;
151  }
152  }
153 
154  printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
155  printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
157 
158  cpu_feature_flag = cpu_get_feature_flags_ecx();
159  aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
160  txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
161  vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
163  "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
164  mode[aes], mode[txt], mode[vt]);
165 }
166 
167 static void report_mch_info(void)
168 {
169  int i;
170  pci_devfn_t dev = SA_DEV_ROOT;
171  uint16_t mchid = get_dev_id(dev);
172  uint8_t mch_revision = get_dev_revision(dev);
173  const char *mch_type = "Unknown";
174 
175  for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
176  if (mch_table[i].mchid == mchid) {
177  mch_type = mch_table[i].name;
178  break;
179  }
180  }
181 
182  printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
183  mchid, mch_revision, mch_type);
184 }
185 
186 static void report_pch_info(void)
187 {
188  int i;
190  uint16_t espiid = get_dev_id(dev);
191  const char *pch_type = "Unknown";
192 
193  for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
194  if (pch_table[i].espiid == espiid) {
195  pch_type = pch_table[i].name;
196  break;
197  }
198  }
199  printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
201 }
202 
203 static void report_igd_info(void)
204 {
205  int i;
206  pci_devfn_t dev = SA_DEV_IGD;
207  uint16_t igdid = get_dev_id(dev);
208  const char *igd_type = "Unknown";
209 
210  for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
211  if (igd_table[i].igdid == igdid) {
212  igd_type = igd_table[i].name;
213  break;
214  }
215  }
216  printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
217  igdid, get_dev_revision(dev), igd_type);
218 }
219 
221 {
222  report_cpu_info();
223  report_mch_info();
224  report_pch_info();
225  report_igd_info();
226 }
cpu_type
Definition: cpu.h:347
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define printk(level,...)
Definition: stdlib.h:16
uint32_t cpu_get_feature_flags_ecx(void)
Definition: cpu_common.c:72
uint32_t cpu_get_cpuid(void)
Definition: cpu_common.c:63
#define CPUID_TIGERLAKE_B0
Definition: cpu_ids.h:49
#define CPUID_TIGERLAKE_A0
Definition: cpu_ids.h:48
#define CPUID_TIGERLAKE_R0
Definition: cpu_ids.h:50
#define CPUID_AES
Definition: msr.h:28
#define CPUID_VMX
Definition: msr.h:24
#define CPUID_SMX
Definition: msr.h:25
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
Definition: pci_ops.h:52
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
Definition: pci_ops.h:46
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
uint32_t get_current_microcode_rev(void)
Definition: microcode.c:112
void report_platform_info(void)
#define PCI_DEVICE_ID
Definition: pci_def.h:9
#define PCI_REVISION_ID
Definition: pci_def.h:41
#define PCI_DID_INTEL_TGP_ESPI_10
Definition: pci_ids.h:2944
#define PCI_DID_INTEL_TGP_ESPI_16
Definition: pci_ids.h:2950
#define PCI_DID_INTEL_TGP_ESPI_9
Definition: pci_ids.h:2943
#define PCI_DID_INTEL_TGL_ID_H_6_1
Definition: pci_ids.h:4022
#define PCI_DID_INTEL_TGP_ESPI_14
Definition: pci_ids.h:2948
#define PCI_DID_INTEL_TGP_ESPI_17
Definition: pci_ids.h:2951
#define PCI_DID_INTEL_TGP_ESPI_6
Definition: pci_ids.h:2940
#define PCI_DID_INTEL_TGP_SUPER_U_ESPI
Definition: pci_ids.h:2930
#define PCI_DID_INTEL_TGP_ESPI_22
Definition: pci_ids.h:2956
#define PCI_DID_INTEL_TGL_GT0
Definition: pci_ids.h:3912
#define PCI_DID_INTEL_TGP_H_ESPI_H570
Definition: pci_ids.h:2963
#define PCI_DID_INTEL_TGL_ID_U_4_2
Definition: pci_ids.h:4019
#define PCI_DID_INTEL_TGP_ESPI_20
Definition: pci_ids.h:2954
#define PCI_DID_INTEL_TGP_ESPI_7
Definition: pci_ids.h:2941
#define PCI_DID_INTEL_TGP_ESPI_15
Definition: pci_ids.h:2949
#define PCI_DID_INTEL_TGL_GT3_ULT
Definition: pci_ids.h:3916
#define PCI_DID_INTEL_TGP_H_ESPI_QM580
Definition: pci_ids.h:2968
#define PCI_DID_INTEL_TGP_ESPI_3
Definition: pci_ids.h:2937
#define PCI_DID_INTEL_TGP_ESPI_24
Definition: pci_ids.h:2958
#define PCI_DID_INTEL_TGL_ID_Y_4_2
Definition: pci_ids.h:4021
#define PCI_DID_INTEL_TGP_BASE_U_ESPI
Definition: pci_ids.h:2932
#define PCI_DID_INTEL_TGP_H_ESPI_HM570
Definition: pci_ids.h:2967
#define PCI_DID_INTEL_TGP_ESPI_26
Definition: pci_ids.h:2960
#define PCI_DID_INTEL_TGP_ESPI_2
Definition: pci_ids.h:2934
#define PCI_DID_INTEL_TGL_GT2_ULT_1
Definition: pci_ids.h:3918
#define PCI_DID_INTEL_TGP_H_ESPI_Z590
Definition: pci_ids.h:2966
#define PCI_DID_INTEL_TGP_PREMIUM_Y_ESPI
Definition: pci_ids.h:2936
#define PCI_DID_INTEL_TGP_H_ESPI_Q570
Definition: pci_ids.h:2964
#define PCI_DID_INTEL_TGL_GT1_H_16
Definition: pci_ids.h:3914
#define PCI_DID_INTEL_TGL_GT1_H_32
Definition: pci_ids.h:3913
#define PCI_DID_INTEL_TGP_H_ESPI_H510
Definition: pci_ids.h:2962
#define PCI_DID_INTEL_TGL_ID_Y_2_2
Definition: pci_ids.h:4020
#define PCI_DID_INTEL_TGL_GT2_ULX
Definition: pci_ids.h:3917
#define PCI_DID_INTEL_TGP_ESPI_8
Definition: pci_ids.h:2942
#define PCI_DID_INTEL_TGP_ESPI_25
Definition: pci_ids.h:2959
#define PCI_DID_INTEL_TGP_ESPI_11
Definition: pci_ids.h:2945
#define PCI_DID_INTEL_TGP_PREMIUM_U_ESPI
Definition: pci_ids.h:2931
#define PCI_DID_INTEL_TGP_ESPI_0
Definition: pci_ids.h:2929
#define PCI_DID_INTEL_TGP_ESPI_12
Definition: pci_ids.h:2946
#define PCI_DID_INTEL_TGP_ESPI_18
Definition: pci_ids.h:2952
#define PCI_DID_INTEL_TGP_ESPI_13
Definition: pci_ids.h:2947
#define PCI_DID_INTEL_TGP_H_ESPI_WM590
Definition: pci_ids.h:2969
#define PCI_DID_INTEL_TGP_ESPI_4
Definition: pci_ids.h:2938
#define PCI_DID_INTEL_TGP_H_ESPI_B560
Definition: pci_ids.h:2961
#define PCI_DID_INTEL_TGP_ESPI_19
Definition: pci_ids.h:2953
#define PCI_DID_INTEL_TGL_ID_U_2_2
Definition: pci_ids.h:4018
#define PCI_DID_INTEL_TGP_SUPER_Y_ESPI
Definition: pci_ids.h:2935
#define PCI_DID_INTEL_TGP_ESPI_21
Definition: pci_ids.h:2955
#define PCI_DID_INTEL_TGP_H_ESPI_W580
Definition: pci_ids.h:2965
#define PCI_DID_INTEL_TGL_ID_H_8_1
Definition: pci_ids.h:4023
#define PCI_DID_INTEL_TGL_GT2_ULT
Definition: pci_ids.h:3915
#define PCI_DID_INTEL_TGP_ESPI_1
Definition: pci_ids.h:2933
#define PCI_DID_INTEL_TGP_ESPI_23
Definition: pci_ids.h:2957
#define PCI_DID_INTEL_TGP_ESPI_5
Definition: pci_ids.h:2939
u32 pci_devfn_t
Definition: pci_type.h:8
u16 mchid
u16 igdid
const char * name
u32 cpuid
u16 espiid
unsigned int cpu_id
Definition: chip.h:47
#define PCH_DEV_ESPI
Definition: pci_devs.h:223
#define SA_DEV_IGD
Definition: pci_devs.h:33
u16 pch_type(void)
Definition: pch.c:20
#define SA_DEV_ROOT
Definition: pci_devs.h:26
static struct @647 pch_table[]
static void report_igd_info(void)
static struct @646 mch_table[]
static void report_mch_info(void)
static uint16_t get_dev_id(pci_devfn_t dev)
static void report_pch_info(void)
static struct @648 igd_table[]
static struct @645 cpu_table[]
static void report_cpu_info(void)
static uint8_t get_dev_revision(pci_devfn_t dev)
unsigned short uint16_t
Definition: stdint.h:11
uint32_t u32
Definition: stdint.h:51
uint16_t u16
Definition: stdint.h:48
unsigned char uint8_t
Definition: stdint.h:8
size_t strlen(const char *src)
Definition: string.c:42
uint32_t ecx
Definition: cpu.h:32
uint32_t ebx
Definition: cpu.h:31
uint32_t edx
Definition: cpu.h:33
uint32_t eax
Definition: cpu.h:30