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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <bootsplash.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <option.h>
#include <intelblocks/irq.h>
#include <intelblocks/lpss.h>
#include <intelblocks/power_limit.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <string.h>
#include <types.h>
#include "chip.h"
Go to the source code of this file.
Macros | |
#define | PCH_SERIAL_IO_INDEX(x) ((x) - 1) |
Functions | |
static uint8_t | get_param_value (const config_t *config, uint32_t dev_offset) |
static void | parse_devicetree (const config_t *config, FSP_S_CONFIG *params) |
static void | ignore_gbe_ltr (void) |
static void | configure_gspi_cs (int idx, const config_t *config, uint8_t *polarity, uint8_t *enable, uint8_t *defaultcs) |
static const SI_PCH_DEVICE_INTERRUPT_CONFIG * | pci_irq_to_fsp (size_t *out_count) |
void | platform_fsp_silicon_init_params_cb (FSPS_UPD *supd) |
__weak void | mainboard_silicon_init_params (FSPS_UPD *supd) |
void | soc_load_logo (FSPS_UPD *supd) |
Variables | |
static const pci_devfn_t | serial_io_dev [] |
static const struct slot_irq_constraints | irq_constraints [] |
Definition at line 212 of file fsp_params.c.
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Definition at line 267 of file fsp_params.c.
References config, spi_cfg::cs_polarity, gspi_get_soc_spi_cfg(), NULL, and SPI_POLARITY_LOW.
Referenced by platform_fsp_silicon_init_params_cb().
Definition at line 214 of file fsp_params.c.
References config, is_devfn_enabled(), PCH_SERIAL_IO_INDEX, PchSerialIoDisabled, PchSerialIoMax, PchSerialIoNotInitialized, PchSerialIoPci, and serial_io_dev.
Referenced by parse_devicetree().
Definition at line 257 of file fsp_params.c.
References IGN_GBE, LTR_IGN, pmc_mmio_regs(), read8(), and write8().
Referenced by platform_fsp_silicon_init_params_cb().
Definition at line 749 of file fsp_params.c.
References BIOS_DEBUG, and printk.
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Definition at line 229 of file fsp_params.c.
References ARRAY_SIZE, config, get_param_value(), params, serial_io_dev, and SOC_INTEL_CML_UART_DEV_MAX.
Referenced by platform_fsp_silicon_init_params_cb().
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Definition at line 289 of file fsp_params.c.
References calloc(), config, pci_irq_entry::devfn, get_cached_pci_irqs(), pci_irq_entry::irq, MIN_PCH_SLOT, pci_irq_entry::next, NULL, PCI_FUNC, PCI_SLOT, and pci_irq_entry::pin.
Referenced by platform_fsp_silicon_init_params_cb().
void platform_fsp_silicon_init_params_cb | ( | FSPS_UPD * | supd | ) |
Definition at line 330 of file fsp_params.c.
References ARRAY_SIZE, assign_pci_irqs(), BIOS_DEBUG, BIOS_INFO, CHIPSET_LOCKDOWN_FSP, config, CONFIG, config_of_soc, configure_gspi_cs(), device, die(), fill_vr_domain_config(), FSP_S_CONFIG, get_lockdown_config(), get_pm_pwr_cyc_dur(), get_uint_option(), ignore_gbe_ltr(), irq_constraints, is_devfn_enabled(), mainboard_silicon_init_params(), memcpy(), memset(), NULL, params, parse_devicetree(), PAVP, PCH_DEVFN_CNViWIFI, PCH_DEVFN_CSE_3, PCH_DEVFN_EMMC, PCH_DEVFN_GBE, PCH_DEVFN_HDA, PCH_DEVFN_SATA, PCH_DEVFN_SDCARD, PCH_DEVFN_UFS, PCH_DEVFN_USBOTG, PCH_DEVFN_XHCI, PCI_FUNC, pci_irq_to_fsp(), PCI_SLOT, PCI_SUBSYSTEM_VENDOR_ID, pcidev_path_on_root(), PCIE_CLK_NOTUSED, PCIE_CLK_RP0, printk, soc_power_limits_config::psys_pmax, SA_DEVFN_IGD, SERIRQ_CONTINUOUS, SERIRQ_OFF, device::subsystem_device, device::subsystem_vendor, vbt_get(), and xdci_can_enable().
void soc_load_logo | ( | FSPS_UPD * | supd | ) |
Definition at line 755 of file fsp_params.c.
References bmp_load_logo().
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Definition at line 24 of file fsp_params.c.
Referenced by platform_fsp_silicon_init_params_cb().
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Definition at line 24 of file fsp_params.c.
Referenced by get_param_value(), and parse_devicetree().