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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <arch/hpet.h>
#include <console/console.h>
#include <console/usb.h>
#include <string.h>
#include <cbmem.h>
#include <cbfs.h>
#include <cf9_reset.h>
#include <ip_checksum.h>
#include <memory_info.h>
#include <mrc_cache.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/dram/ddr3.h>
#include <northbridge/intel/haswell/chip.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <smbios.h>
#include <spd.h>
#include <security/vboot/vboot_common.h>
#include <commonlib/region.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <timestamp.h>
#include <types.h>
#include "pei_data.h"
Go to the source code of this file.
Macros | |
#define | MRC_CACHE_VERSION 1 |
Functions | |
static void | save_mrc_data (struct pei_data *pei_data) |
static void | prepare_mrc_cache (struct pei_data *pei_data) |
static void | report_memory_config (void) |
static void | sdram_initialize (struct pei_data *pei_data) |
Find PEI executable in coreboot filesystem and execute it. More... | |
static uint8_t | nb_get_ecc_type (const uint32_t capid0_a) |
static uint16_t | nb_slots_per_channel (const uint32_t capid0_a) |
static uint16_t | nb_number_of_channels (const uint32_t capid0_a) |
static uint32_t | nb_max_chan_capacity_mib (const uint32_t capid0_a) |
static void | setup_sdram_meminfo (struct pei_data *pei_data) |
static void | copy_spd (struct pei_data *pei_data, struct spd_info *spdi) |
static int | make_channel_disabled_mask (const struct pei_data *pd, int ch) |
static enum pei_usb2_port_location | map_to_pei_usb2_location (const enum usb2_port_location loc) |
static uint8_t | map_to_pei_oc_pin (const uint8_t oc_pin) |
void | perform_raminit (const int s3resume) |
Variables | |
static const char *const | ecc_decoder [] |
Definition at line 282 of file raminit.c.
References spd_info::addresses, ARRAY_SIZE, BIOS_DEBUG, BIOS_ERR, cbfs_map(), CONFIG, die(), memcpy(), printk, pei_data::spd_data, spd_info::spd_index, SPD_LEN, and SPD_MEMORY_DOWN.
Referenced by perform_raminit().
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Definition at line 318 of file raminit.c.
References ch, and pei_data::spd_addresses.
Referenced by perform_raminit().
Definition at line 337 of file raminit.c.
References PEI_USB_OC_PIN_SKIP, and USB_OC_PIN_SKIP.
Referenced by perform_raminit().
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Definition at line 318 of file raminit.c.
Referenced by perform_raminit().
Definition at line 186 of file raminit.c.
References CAPID_ECCDIS, MEMORY_ARRAY_ECC_NONE, and MEMORY_ARRAY_ECC_SINGLE_BIT.
Referenced by setup_sdram_meminfo().
Definition at line 201 of file raminit.c.
References CAPID_DDRSZ, and nb_slots_per_channel().
Referenced by setup_sdram_meminfo().
Definition at line 196 of file raminit.c.
References CAPID_PDCD.
Referenced by setup_sdram_meminfo().
Definition at line 191 of file raminit.c.
References CAPID_DDPCD.
Referenced by nb_max_chan_capacity_mib(), and setup_sdram_meminfo().
void perform_raminit | ( | const int | s3resume | ) |
Definition at line 342 of file raminit.c.
References addr, spd_info::addresses, ARRAY_SIZE, BIOS_CRIT, pei_data::boot_mode, cbmem_recovery(), CONFIG, config_of_soc, copy_spd(), DEFAULT_GPIOBASE, DEFAULT_PMBASE, pei_data::dimm_channel0_disabled, pei_data::dimm_channel1_disabled, northbridge_intel_haswell_config::dq_pins_interleaved, northbridge_intel_haswell_config::ec_present, pei_usb2_port_setting::enable, pei_usb3_port_setting::enable, usb2_port_config::enable, usb3_port_config::enable, device::enabled, get_pch_platform_type(), HPET_BASE_ADDRESS, intel_early_me_status(), pei_usb2_port_setting::length, usb2_port_config::length, pei_usb2_port_setting::location, usb2_port_config::location, mainboard_usb2_ports, mainboard_usb3_ports, make_channel_disabled_mask(), map_to_pei_oc_pin(), map_to_pei_usb2_location(), mb_get_spd_map(), usb2_port_config::oc_pin, usb3_port_config::oc_pin, pei_usb2_port_setting::over_current_pin, pei_usb3_port_setting::over_current_pin, pcidev_on_root(), PEI_USB_OC_PIN_SKIP, PEI_USB_PORT_SKIP, PEI_VERSION, pei_data::pei_version, post_code, printk, save_mrc_data(), sdram_initialize(), setup_sdram_meminfo(), pei_data::spd_addresses, SPD_MEMORY_DOWN, system_reset(), timestamp_add_now(), TS_INITRAM_END, TS_INITRAM_START, pei_data::usb2_ports, pei_data::usb3_ports, and northbridge_intel_haswell_config::usb_xhci_on_resume.
Referenced by mainboard_romstage_entry().
Definition at line 40 of file raminit.c.
References BIOS_DEBUG, mrc_cache_current_mmap_leak(), MRC_CACHE_VERSION, pei_data::mrc_input, pei_data::mrc_input_len, MRC_TRAINING_DATA, NULL, and printk.
Referenced by sdram_initialize().
Definition at line 70 of file raminit.c.
References BIOS_DEBUG, ecc_decoder, MAD_CHNL, MAD_DIMM, MC_BIOS_DATA, mchbar_read32(), NUM_CHANNELS, and printk.
Referenced by sdram_initialize().
Definition at line 33 of file raminit.c.
References mrc_cache_stash_data(), MRC_CACHE_VERSION, pei_data::mrc_output, pei_data::mrc_output_len, and MRC_TRAINING_DATA.
Referenced by perform_raminit().
Find PEI executable in coreboot filesystem and execute it.
pei_data | configuration data for UEFI PEI reference code |
Definition at line 114 of file raminit.c.
References BIOS_DEBUG, BIOS_EMERG, BIOS_ERR, pei_data::boot_mode, cbfs_ro_map(), CONFIG, die(), die_with_post_code, do_putchar(), MC_INIT_STATE_G, mchbar_read32(), pei_data::mrc_input, MRC_REVISION, NULL, post_code, POST_INVALID_VENDOR_BINARY, POST_RESUME_FAILURE, prepare_mrc_cache(), printk, report_memory_config(), system_reset(), pei_data::tx_byte, usbdebug_hw_init(), and version.
Definition at line 225 of file raminit.c.
References dimm_info::bank_locator, dimm_info::bus_width, CAPID0_A, cbmem_add(), CBMEM_ID_MEMINFO, ch, dimm_info::channel_num, DDR3_SPD_SODIMM, dimm_info::ddr_frequency, dimm_info::ddr_type, die(), memory_info::dimm, memory_info::dimm_cnt, dimm_info::dimm_num, dimm_info::dimm_size, memory_info::ecc_type, HOST_BRIDGE, MAD_DIMM, memory_info::max_capacity_mib, MC_BIOS_DATA, mchbar_read32(), memcpy(), MEMORY_BUS_WIDTH_64, MEMORY_TYPE_DDR3, memset(), dimm_info::mod_id, dimm_info::mod_type, dimm_info::module_part_number, nb_get_ecc_type(), nb_max_chan_capacity_mib(), nb_number_of_channels(), nb_slots_per_channel(), NUM_CHANNELS, NUM_SLOTS, memory_info::number_of_devices, pci_read_config32(), dimm_info::rank_per_dimm, dimm_info::serial, pei_data::spd_data, SPD_DIMM_MOD_ID1, SPD_DIMM_MOD_ID2, SPD_DIMM_PART_LEN, SPD_DIMM_PART_NUM, SPD_DIMM_SERIAL_LEN, and SPD_DIMM_SERIAL_NUM.
Referenced by perform_raminit().
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Definition at line 62 of file raminit.c.
Referenced by report_memory_config().