![]() |
coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
|
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <option.h>
#include <types.h>
#include "chip.h"
#include "i82801jx.h"
Go to the source code of this file.
Typedefs | |
typedef struct southbridge_intel_i82801jx_config | config_t |
Functions | |
static void | sata_enable_ahci_mmap (struct device *const dev, const u8 port_map) |
static void | sata_program_indexed (struct device *const dev) |
static void | sata_init (struct device *const dev) |
static void | sata_enable (struct device *dev) |
Variables | |
static struct device_operations | sata_ops |
static const unsigned short | pci_device_ids [] |
static const struct pci_driver pch_sata | __pci_driver |
typedef struct southbridge_intel_i82801jx_config config_t |
Definition at line 197 of file sata.c.
References device::chip_info, config, get_uint_option(), and pci_write_config16().
Definition at line 18 of file sata.c.
References addr, BIOS_DEBUG, PCI_BASE_ADDRESS_5, printk, probe_resource(), read32(), res2mmio(), void(), and write32().
Referenced by sata_init().
Definition at line 126 of file sata.c.
References BIOS_DEBUG, BIOS_ERR, device::chip_info, config, D31F2_IDE_TIM_PRI, D31F2_IDE_TIM_SEC, DEFAULT_GPIOBASE, get_uint_option(), inb(), NULL, PCI_BASE_ADDRESS_5, PCI_CLASS_PROG, PCI_COMMAND, PCI_COMMAND_IO, PCI_COMMAND_MASTER, PCI_COMMAND_MEMORY, pci_read_config16(), pci_write_config16(), pci_write_config32(), pci_write_config8(), printk, sata_enable_ahci_mmap(), and sata_program_indexed().
Definition at line 63 of file sata.c.
References D31F2_SDAT, D31F2_SIDX, pci_read_config32(), pci_write_config32(), and pci_write_config8().
Referenced by sata_init().
|
static |
|
static |
|
static |