12 #include <soc/bootblock.h>
15 #include <soc/pci_devs.h>
16 #include <soc/systemagent.h>
89 "Kabylake-Y iHDCP 2.2 Premium" },
91 "Kabylake-U iHDCP 2.2 Premium" },
93 "Kabylake-U iHDCP 2.2 Base" },
148 static const char *
const mode[] = {
"NOT ",
""};
167 aes = (cpu_feature_flag &
CPUID_AES) ? 1 : 0;
168 txt = (cpu_feature_flag &
CPUID_SMX) ? 1 : 0;
169 vt = (cpu_feature_flag &
CPUID_VMX) ? 1 : 0;
171 "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
172 mode[aes], mode[txt], mode[vt]);
181 const char *mch_type =
"Unknown";
191 mchid, mch_revision, mch_type);
216 const char *igd_type =
"Unknown";
#define printk(level,...)
uint32_t cpu_get_feature_flags_ecx(void)
uint32_t cpu_get_cpuid(void)
#define CPUID_KABYLAKE_Y0
#define CPUID_SKYLAKE_HR0
#define CPUID_KABYLAKE_H0
#define CPUID_KABYLAKE_HA0
#define CPUID_KABYLAKE_HB0
#define CPUID_KABYLAKE_G0
#define CPUID_SKYLAKE_HQ0
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
uint32_t get_current_microcode_rev(void)
void fill_processor_name(char *processor_name)
#define PCI_DID_INTEL_SKL_GT2_SHALM
#define PCI_DID_INTEL_UPT_LP_Y_PREMIUM
#define PCI_DID_INTEL_SKL_GT3_SULTM
#define PCI_DID_INTEL_KBL_ID_H
#define PCI_DID_INTEL_KBL_U_R
#define PCI_DID_INTEL_SKL_ID_H_2
#define PCI_DID_INTEL_UPT_LP_U_PREMIUM
#define PCI_DID_INTEL_SKL_GT4_SHALM
#define PCI_DID_INTEL_SKL_GT4E_SWSTM
#define PCI_DID_INTEL_SKL_GT3FE_SSRVM
#define PCI_DID_INTEL_SPT_H_HM175
#define PCI_DID_INTEL_SPT_H_B150
#define PCI_DID_INTEL_KBL_ID_Y
#define PCI_DID_INTEL_AML_GT2_ULX
#define PCI_DID_INTEL_UPT_H_H310C
#define PCI_DID_INTEL_UPT_H_Z270
#define PCI_DID_INTEL_KBL_GT1_SULTM
#define PCI_DID_INTEL_SKL_ID_H_4
#define PCI_DID_INTEL_KBL_GT1_SSRVM
#define PCI_DID_INTEL_SKL_GT2_SULTM
#define PCI_DID_INTEL_KBL_GT2_DT2P2
#define PCI_DID_INTEL_SPT_LP_U_PREMIUM_HDCP22
#define PCI_DID_INTEL_SKL_ID_U
#define PCI_DID_INTEL_SKL_ID_ULX
#define PCI_DID_INTEL_UPT_H_H270
#define PCI_DID_INTEL_KBL_GT2_SULTM
#define PCI_DID_INTEL_SPT_H_Z170
#define PCI_DID_INTEL_KBL_GT2_SHALM
#define PCI_DID_INTEL_KBL_GT4_SHALM
#define PCI_DID_INTEL_KBL_GT3E_SULTM_1
#define PCI_DID_INTEL_SPT_H_C232
#define PCI_DID_INTEL_SPT_H_C236
#define PCI_DID_INTEL_SKL_ID_S_2
#define PCI_DID_INTEL_KBL_GT1_SHALM_2
#define PCI_DID_INTEL_KBL_GT2_SWSTM
#define PCI_DID_INTEL_UPT_LP_U_BASE
#define PCI_DID_INTEL_SPT_LP_SAMPLE
#define PCI_DID_INTEL_SKL_ID_H_EM
#define PCI_DID_INTEL_KBL_GT2_SSRVM
#define PCI_DID_INTEL_KBL_GT3E_SULTM_2
#define PCI_DID_INTEL_KBL_GT1F_DT2
#define PCI_DID_INTEL_UPT_H_B365
#define PCI_DID_INTEL_KBL_GT2_SULTMR
#define PCI_DID_INTEL_SKL_GT2_SULXM
#define PCI_DID_INTEL_UPT_H_Z370
#define PCI_DID_INTEL_SPT_H_CM238
#define PCI_DID_INTEL_SPT_H_HM170
#define PCI_DID_INTEL_SKL_GT1F_SHALM
#define PCI_DID_INTEL_SKL_ID_Y
#define PCI_DID_INTEL_SPT_H_H170
#define PCI_DID_INTEL_SPT_H_Q170
#define PCI_DID_INTEL_UPT_H_Q250
#define PCI_DID_INTEL_KBL_ID_DT_2
#define PCI_DID_INTEL_KBL_ID_DT
#define PCI_DID_INTEL_SPT_H_H110
#define PCI_DID_INTEL_KBL_GT1_SHALM_1
#define PCI_DID_INTEL_SKL_GT2_DT2P1
#define PCI_DID_INTEL_SPT_LP_U_BASE
#define PCI_DID_INTEL_SKL_GT3E_SULTM_2
#define PCI_DID_INTEL_SKL_GT1F_DT2
#define PCI_DID_INTEL_SPT_H_CM236
#define PCI_DID_INTEL_UPT_LP_SUPER_SKU
#define PCI_DID_INTEL_SKL_GT3E_SULTM_1
#define PCI_DID_INTEL_SPT_H_QM175
#define PCI_DID_INTEL_SPT_H_QM170
#define PCI_DID_INTEL_UPT_H_B250
#define PCI_DID_INTEL_KBL_GT2_SULXM
#define PCI_DID_INTEL_SKL_ID_S_4
#define PCI_DID_INTEL_SPT_LP_U_BASE_HDCP22
#define PCI_DID_INTEL_KBL_ID_U
#define PCI_DID_INTEL_KBL_GT2F_SULTM
#define PCI_DID_INTEL_UPT_H_Q270
#define PCI_DID_INTEL_KBL_ID_S
#define PCI_DID_INTEL_SPT_LP_U_PREMIUM
#define PCI_DID_INTEL_SPT_H_Q150
#define PCI_DID_INTEL_SKL_GT1_SULTM
#define PCI_DID_INTEL_SKL_GT2_SWKSM
#define PCI_DID_INTEL_SPT_LP_Y_PREMIUM
#define PCI_DID_INTEL_SPT_LP_Y_PREMIUM_HDCP22