coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
report_platform.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <arch/cpu.h>
4 #include <device/pci_ops.h>
5 #include <console/console.h>
6 #include <cpu/intel/cpu_ids.h>
7 #include <cpu/intel/microcode.h>
8 #include <cpu/x86/msr.h>
9 #include <cpu/x86/name.h>
10 #include <device/pci.h>
11 #include <device/pci_ids.h>
12 #include <soc/bootblock.h>
13 #include <soc/cpu.h>
14 #include <soc/pch.h>
15 #include <soc/pci_devs.h>
16 #include <soc/systemagent.h>
17 
18 static struct {
20  const char *name;
21 } cpu_table[] = {
22  { CPUID_SKYLAKE_C0, "Skylake C0" },
23  { CPUID_SKYLAKE_D0, "Skylake D0" },
24  { CPUID_SKYLAKE_HQ0, "Skylake H Q0" },
25  { CPUID_SKYLAKE_HR0, "Skylake H R0" },
26  { CPUID_KABYLAKE_G0, "Kabylake G0" },
27  { CPUID_KABYLAKE_H0, "Kabylake H0" },
28  { CPUID_KABYLAKE_Y0, "Kabylake Y0" },
29  { CPUID_KABYLAKE_HA0, "Kabylake H A0" },
30  { CPUID_KABYLAKE_HB0, "Kabylake H B0" },
31 };
32 
33 static struct {
35  const char *name;
36 } mch_table[] = {
37  { PCI_DID_INTEL_SKL_ID_U, "Skylake-U" },
38  { PCI_DID_INTEL_SKL_ID_Y, "Skylake-Y" },
39  { PCI_DID_INTEL_SKL_ID_ULX, "Skylake-ULX" },
40  { PCI_DID_INTEL_SKL_ID_H_4, "Skylake-H (4 Core)" },
41  { PCI_DID_INTEL_SKL_ID_H_EM, "Skylake-H Embedded" },
42  { PCI_DID_INTEL_SKL_ID_H_2, "Skylake-H (2 Core)" },
43  { PCI_DID_INTEL_SKL_ID_S_2, "Skylake-S (2 Core)" },
44  { PCI_DID_INTEL_SKL_ID_S_4, "Skylake-S (4 Core) / Skylake-DT" },
45  { PCI_DID_INTEL_KBL_ID_U, "Kabylake-U" },
46  { PCI_DID_INTEL_KBL_U_R, "Kabylake-R ULT"},
47  { PCI_DID_INTEL_KBL_ID_Y, "Kabylake-Y" },
48  { PCI_DID_INTEL_KBL_ID_H, "Kabylake-H" },
49  { PCI_DID_INTEL_KBL_ID_S, "Kabylake-S" },
50  { PCI_DID_INTEL_KBL_ID_DT, "Kabylake DT" },
51  { PCI_DID_INTEL_KBL_ID_DT_2, "Kabylake DT 2" },
52 };
53 
54 static struct {
56  const char *name;
57 } pch_table[] = {
58  { PCI_DID_INTEL_SPT_LP_SAMPLE, "Skylake LP Sample" },
59  { PCI_DID_INTEL_SPT_LP_U_BASE, "Skylake-U Base" },
60  { PCI_DID_INTEL_SPT_LP_U_PREMIUM, "Skylake-U Premium" },
61  { PCI_DID_INTEL_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" },
62  { PCI_DID_INTEL_SPT_H_H110, "H110" },
63  { PCI_DID_INTEL_SPT_H_H170, "H170" },
64  { PCI_DID_INTEL_SPT_H_Z170, "Z170" },
65  { PCI_DID_INTEL_SPT_H_Q170, "Q170" },
66  { PCI_DID_INTEL_SPT_H_Q150, "Q150" },
67  { PCI_DID_INTEL_SPT_H_B150, "B150" },
68  { PCI_DID_INTEL_SPT_H_C236, "C236" },
69  { PCI_DID_INTEL_SPT_H_C232, "C232" },
70  { PCI_DID_INTEL_SPT_H_QM170, "QM170" },
71  { PCI_DID_INTEL_SPT_H_HM170, "HM170" },
72  { PCI_DID_INTEL_SPT_H_CM236, "CM236" },
73  { PCI_DID_INTEL_SPT_H_HM175, "HM175" },
74  { PCI_DID_INTEL_SPT_H_QM175, "QM175" },
75  { PCI_DID_INTEL_SPT_H_CM238, "CM238" },
76  { PCI_DID_INTEL_UPT_H_Q270, "Q270" },
77  { PCI_DID_INTEL_UPT_H_H270, "H270" },
78  { PCI_DID_INTEL_UPT_H_Z270, "Z270" },
79  { PCI_DID_INTEL_UPT_H_B250, "B250" },
80  { PCI_DID_INTEL_UPT_H_Q250, "Q250" },
81  { PCI_DID_INTEL_UPT_H_Z370, "Z370" },
82  { PCI_DID_INTEL_UPT_H_H310C, "H310C" },
83  { PCI_DID_INTEL_UPT_H_B365, "B365" },
84  { PCI_DID_INTEL_UPT_LP_U_BASE, "Kabylake-U Base" },
85  { PCI_DID_INTEL_UPT_LP_U_PREMIUM, "Kabylake-U Premium" },
86  { PCI_DID_INTEL_UPT_LP_Y_PREMIUM, "Kabylake-Y Premium" },
87  { PCI_DID_INTEL_UPT_LP_SUPER_SKU, "Kabylake Super Sku" },
89  "Kabylake-Y iHDCP 2.2 Premium" },
91  "Kabylake-U iHDCP 2.2 Premium" },
93  "Kabylake-U iHDCP 2.2 Base" },
94 };
95 
96 static struct {
98  const char *name;
99 } igd_table[] = {
100  { PCI_DID_INTEL_SKL_GT1F_DT2, "Skylake DT GT1F" },
101  { PCI_DID_INTEL_SKL_GT1_SULTM, "Skylake ULT GT1" },
102  { PCI_DID_INTEL_SKL_GT1F_SHALM, "Skylake HALO GT1F" },
103  { PCI_DID_INTEL_SKL_GT2_DT2P1, "Skylake DT GT2" },
104  { PCI_DID_INTEL_SKL_GT2_SULTM, "Skylake ULT GT2" },
105  { PCI_DID_INTEL_SKL_GT2_SHALM, "Skylake HALO GT2" },
106  { PCI_DID_INTEL_SKL_GT2_SWKSM, "Skylake Mobile Xeon GT2"},
107  { PCI_DID_INTEL_SKL_GT2_SULXM, "Skylake ULX GT2" },
108  { PCI_DID_INTEL_SKL_GT3_SULTM, "Skylake ULT GT3" },
109  { PCI_DID_INTEL_SKL_GT3E_SULTM_1, "Skylake ULT (15W) GT3E" },
110  { PCI_DID_INTEL_SKL_GT3E_SULTM_2, "Skylake ULT (28W) GT3E" },
111  { PCI_DID_INTEL_SKL_GT3FE_SSRVM, "Skylake Media Server GT3FE" },
112  { PCI_DID_INTEL_SKL_GT4_SHALM, "Skylake HALO GT4" },
113  { PCI_DID_INTEL_SKL_GT4E_SWSTM, "Skylake Workstation GT4E" },
114  { PCI_DID_INTEL_KBL_GT1F_DT2, "Kaby Lake DT GT1F" },
115  { PCI_DID_INTEL_KBL_GT1_SULTM, "Kaby Lake ULT GT1" },
116  { PCI_DID_INTEL_KBL_GT1_SHALM_1, "Kaby Lake HALO GT1" },
117  { PCI_DID_INTEL_KBL_GT1_SHALM_2, "Kaby Lake HALO GT1" },
118  { PCI_DID_INTEL_KBL_GT1_SSRVM, "Kaby Lake SRV GT1" },
119  { PCI_DID_INTEL_KBL_GT2_SSRVM, "Kaby Lake Media Server GT2" },
120  { PCI_DID_INTEL_KBL_GT2_SWSTM, "Kaby Lake Workstation GT2" },
121  { PCI_DID_INTEL_KBL_GT2_SULXM, "Kaby Lake ULX GT2" },
122  { PCI_DID_INTEL_KBL_GT2_SULTM, "Kaby Lake ULT GT2" },
123  { PCI_DID_INTEL_KBL_GT2_SULTMR, "Kaby Lake-R ULT GT2" },
124  { PCI_DID_INTEL_KBL_GT2_SHALM, "Kaby Lake HALO GT2" },
125  { PCI_DID_INTEL_KBL_GT2_DT2P2, "Kaby Lake DT GT2" },
126  { PCI_DID_INTEL_KBL_GT2F_SULTM, "Kaby Lake ULT GT2F" },
127  { PCI_DID_INTEL_KBL_GT3E_SULTM_1, "Kaby Lake ULT (15W) GT3E" },
128  { PCI_DID_INTEL_KBL_GT3E_SULTM_2, "Kaby Lake ULT (28W) GT3E" },
129  { PCI_DID_INTEL_KBL_GT4_SHALM, "Kaby Lake HALO GT4" },
130  { PCI_DID_INTEL_AML_GT2_ULX, "Amberlake ULX GT2" },
131 };
132 
134 {
135  return pci_read_config8(dev, PCI_REVISION_ID);
136 }
137 
139 {
140  return pci_read_config16(dev, PCI_DEVICE_ID);
141 }
142 
143 static void report_cpu_info(void)
144 {
145  u32 i, cpu_id, cpu_feature_flag;
146  char cpu_name[49];
147  int vt, txt, aes;
148  static const char *const mode[] = {"NOT ", ""};
149  const char *cpu_type = "Unknown";
150 
151  fill_processor_name(cpu_name);
152  cpu_id = cpu_get_cpuid();
153 
154  /* Look for string to match the name */
155  for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
156  if (cpu_table[i].cpuid == cpu_id) {
157  cpu_type = cpu_table[i].name;
158  break;
159  }
160  }
161 
162  printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
163  printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
165 
166  cpu_feature_flag = cpu_get_feature_flags_ecx();
167  aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
168  txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
169  vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
171  "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
172  mode[aes], mode[txt], mode[vt]);
173 }
174 
175 static void report_mch_info(void)
176 {
177  int i;
178  pci_devfn_t dev = SA_DEV_ROOT;
179  uint16_t mchid = get_dev_id(dev);
180  uint8_t mch_revision = get_dev_revision(dev);
181  const char *mch_type = "Unknown";
182 
183  for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
184  if (mch_table[i].mchid == mchid) {
185  mch_type = mch_table[i].name;
186  break;
187  }
188  }
189 
190  printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
191  mchid, mch_revision, mch_type);
192 }
193 
194 static void report_pch_info(void)
195 {
196  int i;
197  pci_devfn_t dev = PCH_DEV_LPC;
198  uint16_t lpcid = get_dev_id(dev);
199  const char *pch_type = "Unknown";
200 
201  for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
202  if (pch_table[i].lpcid == lpcid) {
203  pch_type = pch_table[i].name;
204  break;
205  }
206  }
207  printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
209 }
210 
211 static void report_igd_info(void)
212 {
213  int i;
214  pci_devfn_t dev = SA_DEV_IGD;
215  uint16_t igdid = get_dev_id(dev);
216  const char *igd_type = "Unknown";
217 
218  for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
219  if (igd_table[i].igdid == igdid) {
220  igd_type = igd_table[i].name;
221  break;
222  }
223  }
224  printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
225  igdid, get_dev_revision(dev), igd_type);
226 }
227 
229 {
230  report_cpu_info();
231  report_mch_info();
232  report_pch_info();
233  report_igd_info();
234 }
cpu_type
Definition: cpu.h:347
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define printk(level,...)
Definition: stdlib.h:16
uint32_t cpu_get_feature_flags_ecx(void)
Definition: cpu_common.c:72
uint32_t cpu_get_cpuid(void)
Definition: cpu_common.c:63
#define CPUID_KABYLAKE_Y0
Definition: cpu_ids.h:20
#define CPUID_SKYLAKE_HR0
Definition: cpu_ids.h:17
#define CPUID_SKYLAKE_C0
Definition: cpu_ids.h:14
#define CPUID_KABYLAKE_H0
Definition: cpu_ids.h:19
#define CPUID_KABYLAKE_HA0
Definition: cpu_ids.h:21
#define CPUID_KABYLAKE_HB0
Definition: cpu_ids.h:22
#define CPUID_KABYLAKE_G0
Definition: cpu_ids.h:18
#define CPUID_SKYLAKE_D0
Definition: cpu_ids.h:15
#define CPUID_SKYLAKE_HQ0
Definition: cpu_ids.h:16
#define CPUID_AES
Definition: msr.h:28
#define CPUID_VMX
Definition: msr.h:24
#define CPUID_SMX
Definition: msr.h:25
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
Definition: pci_ops.h:52
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
Definition: pci_ops.h:46
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
uint32_t get_current_microcode_rev(void)
Definition: microcode.c:112
void fill_processor_name(char *processor_name)
Definition: name.c:8
void report_platform_info(void)
#define PCI_DEVICE_ID
Definition: pci_def.h:9
#define PCI_REVISION_ID
Definition: pci_def.h:41
#define PCI_DID_INTEL_SKL_GT2_SHALM
Definition: pci_ids.h:3817
#define PCI_DID_INTEL_UPT_LP_Y_PREMIUM
Definition: pci_ids.h:2892
#define PCI_DID_INTEL_SKL_GT3_SULTM
Definition: pci_ids.h:3820
#define PCI_DID_INTEL_KBL_ID_H
Definition: pci_ids.h:3978
#define PCI_DID_INTEL_KBL_U_R
Definition: pci_ids.h:3979
#define PCI_DID_INTEL_SKL_ID_H_2
Definition: pci_ids.h:3970
#define PCI_DID_INTEL_UPT_LP_U_PREMIUM
Definition: pci_ids.h:2891
#define PCI_DID_INTEL_SKL_GT4_SHALM
Definition: pci_ids.h:3824
#define PCI_DID_INTEL_SKL_GT4E_SWSTM
Definition: pci_ids.h:3825
#define PCI_DID_INTEL_SKL_GT3FE_SSRVM
Definition: pci_ids.h:3823
#define PCI_DID_INTEL_SPT_H_HM175
Definition: pci_ids.h:2855
#define PCI_DID_INTEL_SPT_H_B150
Definition: pci_ids.h:2849
#define PCI_DID_INTEL_KBL_ID_Y
Definition: pci_ids.h:3977
#define PCI_DID_INTEL_AML_GT2_ULX
Definition: pci_ids.h:3843
#define PCI_DID_INTEL_UPT_H_H310C
Definition: pci_ids.h:2884
#define PCI_DID_INTEL_UPT_H_Z270
Definition: pci_ids.h:2879
#define PCI_DID_INTEL_KBL_GT1_SULTM
Definition: pci_ids.h:3827
#define PCI_DID_INTEL_SKL_ID_H_4
Definition: pci_ids.h:3971
#define PCI_DID_INTEL_KBL_GT1_SSRVM
Definition: pci_ids.h:3829
#define PCI_DID_INTEL_SKL_GT2_SULTM
Definition: pci_ids.h:3816
#define PCI_DID_INTEL_KBL_GT2_DT2P2
Definition: pci_ids.h:3831
#define PCI_DID_INTEL_SPT_LP_U_PREMIUM_HDCP22
Definition: pci_ids.h:2887
#define PCI_DID_INTEL_SKL_ID_U
Definition: pci_ids.h:3967
#define PCI_DID_INTEL_SKL_ID_ULX
Definition: pci_ids.h:3969
#define PCI_DID_INTEL_UPT_H_H270
Definition: pci_ids.h:2878
#define PCI_DID_INTEL_KBL_GT2_SULTM
Definition: pci_ids.h:3832
#define PCI_DID_INTEL_SPT_H_Z170
Definition: pci_ids.h:2846
#define PCI_DID_INTEL_KBL_GT2_SHALM
Definition: pci_ids.h:3836
#define PCI_DID_INTEL_KBL_GT4_SHALM
Definition: pci_ids.h:3841
#define PCI_DID_INTEL_KBL_GT3E_SULTM_1
Definition: pci_ids.h:3839
#define PCI_DID_INTEL_SPT_H_C232
Definition: pci_ids.h:2851
#define PCI_DID_INTEL_SPT_H_C236
Definition: pci_ids.h:2850
#define PCI_DID_INTEL_SKL_ID_S_2
Definition: pci_ids.h:3972
#define PCI_DID_INTEL_KBL_GT1_SHALM_2
Definition: pci_ids.h:3830
#define PCI_DID_INTEL_KBL_GT2_SWSTM
Definition: pci_ids.h:3837
#define PCI_DID_INTEL_UPT_LP_U_BASE
Definition: pci_ids.h:2890
#define PCI_DID_INTEL_SPT_LP_SAMPLE
Definition: pci_ids.h:2840
#define PCI_DID_INTEL_SKL_ID_H_EM
Definition: pci_ids.h:3975
#define PCI_DID_INTEL_KBL_GT2_SSRVM
Definition: pci_ids.h:3835
#define PCI_DID_INTEL_KBL_GT3E_SULTM_2
Definition: pci_ids.h:3840
#define PCI_DID_INTEL_KBL_GT1F_DT2
Definition: pci_ids.h:3826
#define PCI_DID_INTEL_UPT_H_B365
Definition: pci_ids.h:2885
#define PCI_DID_INTEL_KBL_GT2_SULTMR
Definition: pci_ids.h:3833
#define PCI_DID_INTEL_SKL_GT2_SULXM
Definition: pci_ids.h:3819
#define PCI_DID_INTEL_UPT_H_Z370
Definition: pci_ids.h:2883
#define PCI_DID_INTEL_SPT_H_CM238
Definition: pci_ids.h:2857
#define PCI_DID_INTEL_SPT_H_HM170
Definition: pci_ids.h:2853
#define PCI_DID_INTEL_SKL_GT1F_SHALM
Definition: pci_ids.h:3814
#define PCI_DID_INTEL_SKL_ID_Y
Definition: pci_ids.h:3968
#define PCI_DID_INTEL_SPT_H_H170
Definition: pci_ids.h:2845
#define PCI_DID_INTEL_SPT_H_Q170
Definition: pci_ids.h:2847
#define PCI_DID_INTEL_UPT_H_Q250
Definition: pci_ids.h:2881
#define PCI_DID_INTEL_KBL_ID_DT_2
Definition: pci_ids.h:3980
#define PCI_DID_INTEL_KBL_ID_DT
Definition: pci_ids.h:3981
#define PCI_DID_INTEL_SPT_H_H110
Definition: pci_ids.h:2844
#define PCI_DID_INTEL_KBL_GT1_SHALM_1
Definition: pci_ids.h:3828
#define PCI_DID_INTEL_SKL_GT2_DT2P1
Definition: pci_ids.h:3815
#define PCI_DID_INTEL_SPT_LP_U_BASE
Definition: pci_ids.h:2841
#define PCI_DID_INTEL_SKL_GT3E_SULTM_2
Definition: pci_ids.h:3822
#define PCI_DID_INTEL_SKL_GT1F_DT2
Definition: pci_ids.h:3812
#define PCI_DID_INTEL_SPT_H_CM236
Definition: pci_ids.h:2854
#define PCI_DID_INTEL_UPT_LP_SUPER_SKU
Definition: pci_ids.h:2889
#define PCI_DID_INTEL_SKL_GT3E_SULTM_1
Definition: pci_ids.h:3821
#define PCI_DID_INTEL_SPT_H_QM175
Definition: pci_ids.h:2856
#define PCI_DID_INTEL_SPT_H_QM170
Definition: pci_ids.h:2852
#define PCI_DID_INTEL_UPT_H_B250
Definition: pci_ids.h:2882
#define PCI_DID_INTEL_KBL_GT2_SULXM
Definition: pci_ids.h:3838
#define PCI_DID_INTEL_SKL_ID_S_4
Definition: pci_ids.h:3973
#define PCI_DID_INTEL_SPT_LP_U_BASE_HDCP22
Definition: pci_ids.h:2888
#define PCI_DID_INTEL_KBL_ID_U
Definition: pci_ids.h:3976
#define PCI_DID_INTEL_KBL_GT2F_SULTM
Definition: pci_ids.h:3834
#define PCI_DID_INTEL_UPT_H_Q270
Definition: pci_ids.h:2880
#define PCI_DID_INTEL_KBL_ID_S
Definition: pci_ids.h:3974
#define PCI_DID_INTEL_SPT_LP_U_PREMIUM
Definition: pci_ids.h:2842
#define PCI_DID_INTEL_SPT_H_Q150
Definition: pci_ids.h:2848
#define PCI_DID_INTEL_SKL_GT1_SULTM
Definition: pci_ids.h:3813
#define PCI_DID_INTEL_SKL_GT2_SWKSM
Definition: pci_ids.h:3818
#define PCI_DID_INTEL_SPT_LP_Y_PREMIUM
Definition: pci_ids.h:2843
#define PCI_DID_INTEL_SPT_LP_Y_PREMIUM_HDCP22
Definition: pci_ids.h:2886
u32 pci_devfn_t
Definition: pci_type.h:8
u16 mchid
u16 igdid
const char * name
u32 cpuid
unsigned int cpu_id
Definition: chip.h:47
#define PCH_DEV_LPC
Definition: pci_devs.h:224
#define SA_DEV_IGD
Definition: pci_devs.h:33
u16 lpcid
u16 pch_type(void)
Definition: pch.c:20
#define SA_DEV_ROOT
Definition: pci_devs.h:26
static void report_igd_info(void)
static struct @617 cpu_table[]
static void report_mch_info(void)
static uint16_t get_dev_id(pci_devfn_t dev)
static void report_pch_info(void)
static struct @619 pch_table[]
static struct @620 igd_table[]
static struct @618 mch_table[]
static void report_cpu_info(void)
static uint8_t get_dev_revision(pci_devfn_t dev)
unsigned short uint16_t
Definition: stdint.h:11
uint32_t u32
Definition: stdint.h:51
uint16_t u16
Definition: stdint.h:48
unsigned char uint8_t
Definition: stdint.h:8