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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <amdblocks/acpimmio.h>
#include <device/mmio.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <bootstate.h>
#include <arch/ioapic.h>
#include <device/smbus.h>
#include <pc80/mc146818rtc.h>
#include <pc80/i8254.h>
#include <pc80/i8259.h>
#include <console/console.h>
#include <acpi/acpi.h>
#include <device/pci_ehci.h>
#include "lpc.h"
#include "SBPLATFORM.h"
#include "cfg.h"
#include "chip.h"
#include "sb_cimx.h"
#include "smbus.h"
#include "fan.h"
#include "pci_devs.h"
#include <southbridge/amd/common/amd_pci_util.h>
Go to the source code of this file.
Macros | |
#define | HOST_CAP 0x00 /* host capabilities */ |
#define | HOST_CTL 0x04 /* global host control */ |
#define | HOST_IRQ_STAT 0x08 /* interrupt status */ |
#define | HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ |
#define | HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ |
Functions | |
static u32 | sb800_callout_entry (u32 func, u32 data, void *config) |
Entry point of Southbridge CIMx callout. More... | |
static void | ahci_raid_init (struct device *dev) |
static void | lpc_init (struct device *dev) |
static const char * | lpc_acpi_name (const struct device *dev) |
static void | sb800_init (void *chip_info) |
Fill build time defaults. More... | |
void | sb_Before_Pci_Init (void) |
South Bridge CIMx ramstage entry point wrapper. More... | |
void | sb_After_Pci_Init (void) |
void | sb_Mid_Post_Init (void) |
void | sb_Late_Post (void) |
void | sb_Before_Pci_Restore_Init (void) |
void | sb_After_Pci_Restore_Init (void) |
static void | set_pci_irqs (void *unused) |
BOOT_STATE_INIT_ENTRY (BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL) | |
static void | sb800_enable (struct device *dev) |
SB Cimx entry point sbBeforePciInit wrapper. More... | |
Variables | |
static AMDSBCFG | sb_late_cfg |
static AMDSBCFG * | sb_config = &sb_late_cfg |
static struct device_operations | lpc_ops |
static const struct pci_driver lpc_driver | __pci_driver |
static struct device_operations | sata_ops |
static struct device_operations | usb_ops |
static struct device_operations | azalia_ops |
static struct device_operations | gec_ops |
struct chip_operations | southbridge_amd_cimx_sb800_ops |
#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ |
Definition at line 69 of file late.c.
References BIOS_DEBUG, BIOS_WARNING, device::command, HOST_CAP, HOST_CTL, HOST_CTL_AHCI_EN, HOST_PORTS_IMPL, PCI_BASE_ADDRESS_5, PCI_CLASS_DEVICE, PCI_CLASS_STORAGE_RAID, PCI_CLASS_STORAGE_SATA, PCI_COMMAND, PCI_COMMAND_MASTER, PCI_INTERRUPT_LINE, pci_read_config16(), pci_read_config32(), pci_read_config8(), pci_write_config8(), printk, read32(), val, and write32().
BOOT_STATE_INIT_ENTRY | ( | BS_DEV_ENABLE | , |
BS_ON_ENTRY | , | ||
set_pci_irqs | , | ||
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Definition at line 105 of file late.c.
References BIOS_DEBUG, cmos_check_update_date(), cmos_init(), printk, setup_i8254(), and setup_i8259().
Entry point of Southbridge CIMx callout.
prototype UINT32 (SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void pConfig)
[in] | func | Southbridge CIMx Function ID. |
[in] | data | Southbridge Input Data. |
[in] | config | Southbridge configuration structure pointer. |
Definition at line 41 of file late.c.
References BIOS_DEBUG, and printk.
Referenced by sb800_init().
SB Cimx entry point sbBeforePciInit wrapper.
Definition at line 316 of file late.c.
References acpi_is_wakeup_s3(), AZALIA_AUTO, AZALIA_DISABLE, southbridge_amd_cimx_sb800_config::boot_switch_sata_ide, device::chip_info, pci_path::devfn, device, southbridge_amd_cimx_sb800_config::disconnect_pcib, device::enabled, southbridge_amd_cimx_sb800_config::gpp_configuration, init_sb800_IMC_fans(), init_sb800_MANUAL_fans(), device::path, device_path::pci, PCI_DEVFN, pm_read8(), pm_write8(), sb_Before_Pci_Init(), sb_Before_Pci_Restore_Init(), sb_config, setup_ioapic(), device::sibling, and VIO_APIC_VADDR.
Fill build time defaults.
Definition at line 239 of file late.c.
References abcfg_reg, BIOS_DEBUG, printk, sb800_callout_entry(), sb800_cimx_config(), and sb_config.
Definition at line 259 of file late.c.
References BIOS_DEBUG, printk, and sb_config.
Referenced by platform_BeforeInitMid().
Definition at line 287 of file late.c.
References BIOS_DEBUG, printk, and sb_config.
South Bridge CIMx ramstage entry point wrapper.
Definition at line 252 of file late.c.
References BIOS_DEBUG, printk, and sb_config.
Referenced by sb800_enable().
Definition at line 280 of file late.c.
References BIOS_DEBUG, printk, and sb_config.
Referenced by sb800_enable().
Definition at line 273 of file late.c.
References BIOS_DEBUG, printk, and sb_config.
Referenced by platform_AfterInitLate().
Definition at line 266 of file late.c.
References BIOS_DEBUG, printk, and sb_config.
Referenced by platform_BeforeInitMid().
Definition at line 298 of file late.c.
References write_pci_cfg_irqs(), and write_pci_int_table().
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Definition at line 29 of file late.c.
Referenced by init_sb800_IMC_fans(), sb800_cimx_config(), sb800_enable(), sb800_init(), sb_After_Pci_Init(), sb_After_Pci_Restore_Init(), sb_Before_Pci_Init(), sb_Before_Pci_Restore_Init(), sb_Late_Post(), and sb_Mid_Post_Init().
struct chip_operations southbridge_amd_cimx_sb800_ops |
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