coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
raminit_mrc.c File Reference
#include <arch/hpet.h>
#include <console/console.h>
#include <console/usb.h>
#include <cf9_reset.h>
#include <string.h>
#include <device/device.h>
#include <device/dram/ddr3.h>
#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cbmem.h>
#include <cbfs.h>
#include <ip_checksum.h>
#include <pc80/mc146818rtc.h>
#include <device/pci_def.h>
#include <lib.h>
#include <mrc_cache.h>
#include <spd.h>
#include <smbios.h>
#include <stddef.h>
#include <stdint.h>
#include <timestamp.h>
#include "raminit.h"
#include "pei_data.h"
#include "sandybridge.h"
#include "chip.h"
#include <security/vboot/vboot_common.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <memory_info.h>
#include <southbridge/intel/bd82x6x/me.h>
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Data Structures

struct  mrc_var_data
 

Macros

#define CMOS_OFFSET_MRC_SEED   152
 
#define CMOS_OFFSET_MRC_SEED_S3   156
 
#define CMOS_OFFSET_MRC_SEED_CHK   160
 
#define MRC_CACHE_VERSION   0
 
#define DCACHE_RAM_MRC_VAR_BASE
 

Functions

static void save_mrc_data (struct pei_data *pei_data)
 
static void prepare_mrc_cache (struct pei_data *pei_data)
 
static void sdram_initialize (struct pei_data *pei_data)
 Find PEI executable in coreboot filesystem and execute it. More...
 
static void northbridge_fill_pei_data (struct pei_data *pei_data)
 
static void southbridge_fill_pei_data (struct pei_data *pei_data)
 
static void devicetree_fill_pei_data (struct pei_data *pei_data)
 
static void disable_p2p (void)
 
static void setup_sdram_meminfo (struct pei_data *pei_data)
 
void perform_raminit (int s3resume)
 

Variables

struct mrc_var_data __packed
 

Macro Definition Documentation

◆ CMOS_OFFSET_MRC_SEED

#define CMOS_OFFSET_MRC_SEED   152

Definition at line 45 of file raminit_mrc.c.

◆ CMOS_OFFSET_MRC_SEED_CHK

#define CMOS_OFFSET_MRC_SEED_CHK   160

Definition at line 47 of file raminit_mrc.c.

◆ CMOS_OFFSET_MRC_SEED_S3

#define CMOS_OFFSET_MRC_SEED_S3   156

Definition at line 46 of file raminit_mrc.c.

◆ DCACHE_RAM_MRC_VAR_BASE

#define DCACHE_RAM_MRC_VAR_BASE
Value:
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \
+ CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000)

Definition at line 222 of file raminit_mrc.c.

◆ MRC_CACHE_VERSION

#define MRC_CACHE_VERSION   0

Definition at line 50 of file raminit_mrc.c.

Function Documentation

◆ devicetree_fill_pei_data()

◆ disable_p2p()

static void disable_p2p ( void  )
static

Definition at line 313 of file raminit_mrc.c.

References device::enabled, FD, PCH_DISABLE_P2P, pcidev_on_root(), and RCBA32.

Referenced by perform_raminit().

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◆ northbridge_fill_pei_data()

static void northbridge_fill_pei_data ( struct pei_data pei_data)
static

◆ perform_raminit()

◆ prepare_mrc_cache()

◆ save_mrc_data()

◆ sdram_initialize()

static void sdram_initialize ( struct pei_data pei_data)
static

◆ setup_sdram_meminfo()

◆ southbridge_fill_pei_data()

static void southbridge_fill_pei_data ( struct pei_data pei_data)
static

Definition at line 252 of file raminit_mrc.c.

References DEFAULT_GPIOBASE, DEFAULT_PMBASE, DEFAULT_RCBA, device::enabled, pei_data::gbe_enable, pei_data::gpiobase, pcidev_on_root(), pei_data::pmbase, pei_data::rcba, pei_data::smbusbar, pei_data::wdbbar, and pei_data::wdbsize.

Referenced by perform_raminit().

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Variable Documentation

◆ __packed