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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <device/mmio.h>
#include <assert.h>
#include <bootstate.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <intelblocks/cfg.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpss.h>
#include <intelblocks/spi.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <string.h>
#include <timer.h>
Go to the source code of this file.
Data Structures | |
struct | gspi_ctrlr_params |
Macros | |
#define | SSCR0 0x0 /* SSP Control Register 0 */ |
#define | SSCR0_EDSS_0 (0 << 20) |
#define | SSCR0_EDSS_1 (1 << 20) |
#define | SSCR0_SCR_SHIFT (8) |
#define | SSCR0_SCR_MASK (0xFFF) |
#define | SSCR0_SSE_DISABLE (0 << 7) |
#define | SSCR0_SSE_ENABLE (1 << 7) |
#define | SSCR0_ECS_ON_CHIP (0 << 6) |
#define | SSCR0_FRF_MOTOROLA (0 << 4) |
#define | SSCR0_DSS_SHIFT (0) |
#define | SSCR0_DSS_MASK (0xF) |
#define | SSCR1 0x4 /* SSP Control Register 1 */ |
#define | SSCR1_IFS_LOW (0 << 16) |
#define | SSCR1_IFS_HIGH (1 << 16) |
#define | SSCR1_SPH_FIRST (0 << 4) |
#define | SSCR1_SPH_SECOND (1 << 4) |
#define | SSCR1_SPO_LOW (0 << 3) |
#define | SSCR1_SPO_HIGH (1 << 3) |
#define | SSSR 0x8 /* SSP Status Register */ |
#define | SSSR_TUR (1 << 21) /* Tx FIFO underrun */ |
#define | SSSR_TINT (1 << 19) /* Rx Time-out interrupt */ |
#define | SSSR_PINT |
#define | SSSR_ROR (1 << 7) /* Rx FIFO Overrun */ |
#define | SSSR_BSY (1 << 4) /* SSP Busy */ |
#define | SSSR_RNE (1 << 3) /* Receive FIFO not empty */ |
#define | SSSR_TNF (1 << 2) /* Transmit FIFO not full */ |
#define | SSDR 0x10 /* SSP Data Register */ |
#define | SSTO 0x28 /* SSP Time out */ |
#define | SITF 0x44 /* SPI Transmit FIFO */ |
#define | SITF_LEVEL_SHIFT (16) |
#define | SITF_LEVEL_MASK (0x3f) |
#define | SITF_LWM_SHIFT (8) |
#define | SITF_LWM_MASK (0x3f) |
#define | SITF_LWM(x) ((((x) - 1) & SITF_LWM_MASK) << SITF_LWM_SHIFT) |
#define | SITF_HWM_SHIFT (0) |
#define | SITF_HWM_MASK (0x3f) |
#define | SITF_HWM(x) ((((x) - 1) & SITF_HWM_MASK) << SITF_HWM_SHIFT) |
#define | SIRF 0x48 /* SPI Receive FIFO */ |
#define | SIRF_LEVEL_SHIFT (8) |
#define | SIRF_LEVEL_MASK (0x3f) |
#define | SIRF_WM_SHIFT (0) |
#define | SIRF_WM_MASK (0x3f) |
#define | SIRF_WM(x) ((((x) - 1) & SIRF_WM_MASK) << SIRF_WM_SHIFT) |
#define | CLOCKS 0x200 /* Clocks */ |
#define | CLOCKS_UPDATE (1 << 31) |
#define | CLOCKS_N_SHIFT (16) |
#define | CLOCKS_N_MASK (0x7fff) |
#define | CLOCKS_M_SHIFT (1) |
#define | CLOCKS_M_MASK (0x7fff) |
#define | CLOCKS_DISABLE (0 << 0) |
#define | CLOCKS_ENABLE (1 << 0) |
#define | RESETS 0x204 /* Resets */ |
#define | DMA_RESET (0 << 2) |
#define | DMA_ACTIVE (1 << 2) |
#define | CTRLR_RESET (0 << 0) |
#define | CTRLR_ACTIVE (3 << 0) |
#define | ACTIVELTR_VALUE 0x210 /* Active LTR */ |
#define | IDLELTR_VALUE 0x214 /* Idle LTR Value */ |
#define | TX_BIT_COUNT 0x218 /* Tx Bit Count */ |
#define | RX_BIT_COUNT 0x21c /* Rx Bit Count */ |
#define | SSP_REG 0x220 /* SSP Reg */ |
#define | DMA_FINISH_DISABLE (1 << 0) |
#define | SPI_CS_CONTROL 0x224 /* SPI CS Control */ |
#define | CS_0_POL_SHIFT (12) |
#define | CS_0_POL_MASK (1 << CS_0_POL_SHIFT) |
#define | CS_POL_LOW (0) |
#define | CS_POL_HIGH (1) |
#define | CS_0 (0 << 8) |
#define | CS_STATE_SHIFT (1) |
#define | CS_STATE_MASK (1 << CS_STATE_SHIFT) |
#define | CS_V1_STATE_LOW (0) |
#define | CS_V1_STATE_HIGH (1) |
#define | CS_MODE_HW (0 << 0) |
#define | CS_MODE_SW (1 << 0) |
#define | GSPI_DATA_BIT_LENGTH (8) |
#define | GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB) |
Enumerations | |
enum | cs_assert { CS_ASSERT , CS_DEASSERT } |
Variables | |
static uintptr_t | gspi_base [CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] |
const struct spi_ctrlr | gspi_ctrlr |
#define CS_0_POL_MASK (1 << CS_0_POL_SHIFT) |
#define CS_STATE_MASK (1 << CS_STATE_SHIFT) |
#define SIRF_WM | ( | x | ) | ((((x) - 1) & SIRF_WM_MASK) << SIRF_WM_SHIFT) |
#define SITF_HWM | ( | x | ) | ((((x) - 1) & SITF_HWM_MASK) << SITF_HWM_SHIFT) |
#define SITF_LWM | ( | x | ) | ((((x) - 1) & SITF_LWM_MASK) << SITF_LWM_SHIFT) |
#define SSSR_PINT |
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Definition at line 383 of file gspi.c.
References CS_0_POL_MASK, CS_STATE_MASK, CS_STATE_SHIFT, gspi_csctrl_state(), gspi_read_mmio_reg(), gspi_write_mmio_reg(), and SPI_CS_CONTROL.
Referenced by gspi_cs_change().
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Definition at line 638 of file gspi.c.
References gspi_ctrlr_params::bytesin, gspi_ctrlr_params::bytesout, gspi_read_data(), gspi_read_dummy(), gspi_rx_fifo_empty(), gspi_rx_fifo_overrun(), gspi_tx_fifo_full(), gspi_write_data(), gspi_write_dummy(), and void().
BOOT_STATE_INIT_ENTRY | ( | BS_DEV_RESOURCES | , |
BS_ON_EXIT | , | ||
gspi_clear_cached_base | , | ||
NULL | |||
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Definition at line 216 of file gspi.c.
References DEVTREE_CONST, device::enabled, GSPI_BUS_BASE, gspi_get_base_addr(), gspi_get_early_base(), gspi_set_base_addr(), gspi_soc_bus_to_devfn(), and pcidev_path_on_root().
Referenced by gspi_get_bus_base_addr().
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Definition at line 421 of file gspi.c.
References CS_ASSERT, and gspi_cs_change().
Definition at line 397 of file gspi.c.
References __gspi_cs_change(), spi_slave::bus, gspi_ctrlr_params_init(), and params.
Referenced by gspi_cs_assert(), and gspi_cs_deassert().
Definition at line 426 of file gspi.c.
References CS_DEASSERT, and gspi_cs_change().
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Definition at line 375 of file gspi.c.
References CONFIG, gspi_csctrl_polarity_v1(), and gspi_csctrl_polarity_v2().
Referenced by gspi_ctrlr_setup().
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Definition at line 367 of file gspi.c.
References CS_POL_HIGH, CS_POL_LOW, and SPI_POLARITY_LOW.
Referenced by gspi_csctrl_polarity().
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Definition at line 359 of file gspi.c.
References CS_POL_HIGH, CS_POL_LOW, and SPI_POLARITY_LOW.
Referenced by gspi_csctrl_polarity().
Definition at line 351 of file gspi.c.
References CONFIG, gspi_csctrl_state_v1(), and gspi_csctrl_state_v2().
Referenced by __gspi_cs_change(), and gspi_ctrlr_setup().
Definition at line 337 of file gspi.c.
References CS_ASSERT, CS_POL_HIGH, CS_V1_STATE_HIGH, and CS_V1_STATE_LOW.
Referenced by gspi_csctrl_state().
Definition at line 332 of file gspi.c.
Referenced by gspi_csctrl_state().
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Definition at line 617 of file gspi.c.
References BIOS_ERR, gspi_ctrlr_params::gspi_bus, gspi_read_byte(), gspi_rx_fifo_empty(), printk, stopwatch_expired(), and stopwatch_init_msecs_expire().
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Definition at line 295 of file gspi.c.
References BIOS_ERR, gspi_ctrlr_params::gspi_bus, gspi_get_bus_base_addr(), gspi_spi_to_gspi_bus(), memset(), gspi_ctrlr_params::mmio_base, printk, and spi_bus.
Referenced by gspi_cs_change(), and gspi_ctrlr_setup().
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Definition at line 444 of file gspi.c.
References assert, BIOS_ERR, spi_slave::bus, spi_cfg::clk_phase, spi_cfg::clk_polarity, CLOCKS, CLOCKS_ENABLE, CLOCKS_M_SHIFT, CLOCKS_N_SHIFT, CLOCKS_UPDATE, spi_slave::cs, CS_0, CS_0_POL_SHIFT, CS_DEASSERT, CS_MODE_SW, spi_cfg::cs_polarity, CS_STATE_SHIFT, CTRLR_ACTIVE, DMA_RESET, gspi_ctrlr_params::gspi_bus, gspi_csctrl_polarity(), gspi_csctrl_state(), gspi_ctrlr_params_init(), GSPI_DATA_BIT_LENGTH, gspi_get_clk_div(), gspi_get_soc_spi_cfg(), gspi_soc_bus_to_devfn(), gspi_write_mmio_reg(), lpss_set_power_state(), params, PCI_DEV, PCI_FUNC, PCI_SLOT, printk, RESETS, SIRF, SIRF_WM, SITF, SITF_HWM, SITF_LWM, SPI_CLOCK_PHASE_FIRST, SPI_CS_CONTROL, SPI_POLARITY_LOW, SSCR0, SSCR0_DSS_SHIFT, SSCR0_ECS_ON_CHIP, SSCR0_EDSS_0, SSCR0_FRF_MOTOROLA, SSCR0_SCR_SHIFT, SSCR0_SSE_DISABLE, SSCR0_SSE_ENABLE, SSCR1, SSCR1_IFS_HIGH, SSCR1_IFS_LOW, SSCR1_SPH_FIRST, SSCR1_SPH_SECOND, SSCR1_SPO_HIGH, SSCR1_SPO_LOW, STATE_D0, and udelay().
Definition at line 167 of file gspi.c.
References ALIGN_DOWN, PCI_BASE_ADDRESS_0, and pci_read_config32().
Referenced by gspi_calc_base_addr().
Definition at line 252 of file gspi.c.
References gspi_base, and gspi_calc_base_addr().
Referenced by gspi_ctrlr_params_init().
Definition at line 243 of file gspi.c.
References gspi_get_cfg(), and gspi_cfg::speed_mhz.
Referenced by gspi_get_clk_div().
Definition at line 108 of file gspi.c.
References chip_get_common_soc_structure(), and soc_intel_common_config::gspi.
Referenced by gspi_get_bus_clk_mhz().
Definition at line 431 of file gspi.c.
References assert, DIV_ROUND_UP, gspi_ctrlr_params::gspi_bus, gspi_get_bus_clk_mhz(), and SSCR0_SCR_MASK.
Referenced by gspi_ctrlr_setup().
Definition at line 102 of file gspi.c.
References EARLY_GSPI_BASE_ADDRESS.
Referenced by gspi_calc_base_addr().
Definition at line 409 of file gspi.c.
References spi_cfg::clk_phase, spi_cfg::clk_polarity, spi_cfg::cs_polarity, spi_cfg::data_bit_length, GSPI_DATA_BIT_LENGTH, SPI_4_WIRE_MODE, SPI_CLOCK_PHASE_FIRST, SPI_POLARITY_LOW, and spi_cfg::wire_mode.
Referenced by configure_gspi_cs(), and gspi_ctrlr_setup().
Definition at line 181 of file gspi.c.
References spi_ctrlr_buses::bus_end, spi_ctrlr_buses::bus_start, spi_ctrlr_buses::ctrlr, gspi_ctrlr, spi_ctrlr_bus_map, and spi_ctrlr_bus_map_count.
Referenced by gspi_spi_to_gspi_bus().
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Definition at line 580 of file gspi.c.
References gspi_read_mmio_reg(), and SSDR.
Referenced by gspi_ctrlr_flush(), gspi_read_data(), and gspi_read_dummy().
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Definition at line 591 of file gspi.c.
References gspi_ctrlr_params::bytesin, gspi_read_byte(), and gspi_ctrlr_params::in.
Referenced by __gspi_xfer().
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Definition at line 605 of file gspi.c.
References gspi_ctrlr_params::bytesin, and gspi_read_byte().
Referenced by __gspi_xfer().
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Definition at line 281 of file gspi.c.
References assert, gspi_ctrlr_params::mmio_base, offset, and read32().
Referenced by __gspi_cs_change(), gspi_read_byte(), and gspi_read_status().
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Definition at line 547 of file gspi.c.
References gspi_read_mmio_reg(), and SSSR.
Referenced by gspi_rx_fifo_empty(), gspi_rx_fifo_overrun(), and gspi_tx_fifo_full().
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Definition at line 558 of file gspi.c.
References gspi_read_status(), and SSSR_RNE.
Referenced by __gspi_xfer(), and gspi_ctrlr_flush().
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Definition at line 568 of file gspi.c.
References BIOS_ERR, gspi_ctrlr_params::gspi_bus, gspi_read_status(), printk, and SSSR_ROR.
Referenced by __gspi_xfer().
Definition at line 172 of file gspi.c.
References base, PCI_BASE_ADDRESS_0, PCI_COMMAND, PCI_COMMAND_MASTER, PCI_COMMAND_MEMORY, and pci_write_config32().
Referenced by gspi_calc_base_addr().
Definition at line 200 of file gspi.c.
References gspi_read_bus_range(), and spi_bus.
Referenced by gspi_ctrlr_params_init().
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Definition at line 563 of file gspi.c.
References gspi_read_status(), and SSSR_TNF.
Referenced by __gspi_xfer().
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Definition at line 586 of file gspi.c.
References gspi_write_mmio_reg(), and SSDR.
Referenced by gspi_write_data(), and gspi_write_dummy().
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Definition at line 598 of file gspi.c.
References gspi_ctrlr_params::bytesout, gspi_write_byte(), and gspi_ctrlr_params::out.
Referenced by __gspi_xfer().
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Definition at line 611 of file gspi.c.
References gspi_ctrlr_params::bytesout, and gspi_write_byte().
Referenced by __gspi_xfer().
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Definition at line 288 of file gspi.c.
References assert, gspi_ctrlr_params::mmio_base, offset, value, and write32().
Referenced by __gspi_cs_change(), gspi_clear_status(), gspi_ctrlr_setup(), and gspi_write_byte().
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Definition at line 251 of file gspi.c.
Referenced by gspi_clear_cached_base(), and gspi_get_bus_base_addr().
const struct spi_ctrlr gspi_ctrlr |
Definition at line 678 of file gspi.c.
Referenced by gspi_read_bus_range().