coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
report_platform.c
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <arch/cpu.h>
4 #include <device/pci_ops.h>
5 #include <console/console.h>
6 #include <cpu/intel/cpu_ids.h>
7 #include <cpu/intel/microcode.h>
8 #include <cpu/x86/msr.h>
9 #include <device/pci.h>
10 #include <device/pci_ids.h>
11 #include <soc/bootblock.h>
12 #include <soc/pch.h>
13 #include <soc/pci_devs.h>
14 #include <string.h>
15 
16 static struct {
18  const char *name;
19 } cpu_table[] = {
20  { CPUID_ICELAKE_A0, "Icelake A0" },
21  { CPUID_ICELAKE_B0, "Icelake B0" },
22 };
23 
24 static struct {
26  const char *name;
27 } mch_table[] = {
28  { PCI_DID_INTEL_ICL_ID_U, "Icelake-U" },
29  { PCI_DID_INTEL_ICL_ID_U_2_2, "Icelake-U-2-2" },
30  { PCI_DID_INTEL_ICL_ID_Y, "Icelake-Y" },
31  { PCI_DID_INTEL_ICL_ID_Y_2, "Icelake-Y-2" },
32 };
33 
34 static struct {
36  const char *name;
37 } pch_table[] = {
38  { PCI_DID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" },
39  { PCI_DID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" },
40  { PCI_DID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" },
41  { PCI_DID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" },
42  { PCI_DID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" },
43  { PCI_DID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" },
44  { PCI_DID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" },
45 };
46 
47 static struct {
49  const char *name;
50 } igd_table[] = {
51  { PCI_DID_INTEL_ICL_GT0_ULT, "Icelake ULT GT0" },
52  { PCI_DID_INTEL_ICL_GT0_5_ULT, "Icelake ULT GT0.5" },
53  { PCI_DID_INTEL_ICL_GT1_ULT, "Icelake U GT1" },
54  { PCI_DID_INTEL_ICL_GT2_ULX_0, "Icelake Y GT2" },
55  { PCI_DID_INTEL_ICL_GT2_ULX_1, "Icelake Y GT2_1" },
56  { PCI_DID_INTEL_ICL_GT2_ULT_1, "Icelake U GT2_1" },
57  { PCI_DID_INTEL_ICL_GT2_ULX_2, "Icelake Y GT2_2" },
58  { PCI_DID_INTEL_ICL_GT2_ULT_2, "Icelake U GT2_2" },
59  { PCI_DID_INTEL_ICL_GT2_ULX_3, "Icelake Y GT2_3" },
60  { PCI_DID_INTEL_ICL_GT2_ULT_3, "Icelake U GT2_3" },
61  { PCI_DID_INTEL_ICL_GT2_ULX_4, "Icelake Y GT2_4" },
62  { PCI_DID_INTEL_ICL_GT2_ULT_4, "Icelake U GT2_4" },
63  { PCI_DID_INTEL_ICL_GT2_ULX_5, "Icelake Y GT2_5" },
64  { PCI_DID_INTEL_ICL_GT2_ULT_5, "Icelake U GT2_5" },
65  { PCI_DID_INTEL_ICL_GT3_ULT, "Icelake U GT3" },
66 };
67 
69 {
70  return pci_read_config8(dev, PCI_REVISION_ID);
71 }
72 
74 {
75  return pci_read_config16(dev, PCI_DEVICE_ID);
76 }
77 
78 static void report_cpu_info(void)
79 {
80  struct cpuid_result cpuidr;
81  u32 i, index, cpu_id, cpu_feature_flag;
82  const char cpu_not_found[] = "Platform info not available";
83  const char *cpu_name = cpu_not_found; /* 48 bytes are reported */
84  int vt, txt, aes;
85  static const char *const mode[] = {"NOT ", ""};
86  const char *cpu_type = "Unknown";
87  u32 p[13];
88 
89  index = 0x80000000;
90  cpuidr = cpuid(index);
91  if (cpuidr.eax >= 0x80000004) {
92  int j = 0;
93 
94  for (i = 2; i <= 4; i++) {
95  cpuidr = cpuid(index + i);
96  p[j++] = cpuidr.eax;
97  p[j++] = cpuidr.ebx;
98  p[j++] = cpuidr.ecx;
99  p[j++] = cpuidr.edx;
100  }
101  p[12] = 0;
102  cpu_name = (char *)p;
103 
104  /* Skip leading spaces in CPU name string */
105  while (cpu_name[0] == ' ' && strlen(cpu_name) > 0)
106  cpu_name++;
107  }
108 
109  cpu_id = cpu_get_cpuid();
110 
111  /* Look for string to match the name */
112  for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
113  if (cpu_table[i].cpuid == cpu_id) {
114  cpu_type = cpu_table[i].name;
115  break;
116  }
117  }
118 
119  printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
120  printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
122 
123  cpu_feature_flag = cpu_get_feature_flags_ecx();
124  aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
125  txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
126  vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
128  "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
129  mode[aes], mode[txt], mode[vt]);
130 }
131 
132 static void report_mch_info(void)
133 {
134  int i;
135  pci_devfn_t dev = SA_DEV_ROOT;
136  uint16_t mchid = get_dev_id(dev);
137  uint8_t mch_revision = get_dev_revision(dev);
138  const char *mch_type = "Unknown";
139 
140  for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
141  if (mch_table[i].mchid == mchid) {
142  mch_type = mch_table[i].name;
143  break;
144  }
145  }
146 
147  printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
148  mchid, mch_revision, mch_type);
149 }
150 
151 static void report_pch_info(void)
152 {
153  int i;
155  uint16_t espiid = get_dev_id(dev);
156  const char *pch_type = "Unknown";
157 
158  for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
159  if (pch_table[i].espiid == espiid) {
160  pch_type = pch_table[i].name;
161  break;
162  }
163  }
164  printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
166 }
167 
168 static void report_igd_info(void)
169 {
170  int i;
171  pci_devfn_t dev = SA_DEV_IGD;
172  uint16_t igdid = get_dev_id(dev);
173  const char *igd_type = "Unknown";
174 
175  for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
176  if (igd_table[i].igdid == igdid) {
177  igd_type = igd_table[i].name;
178  break;
179  }
180  }
181  printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
182  igdid, get_dev_revision(dev), igd_type);
183 }
184 
186 {
187  report_cpu_info();
188  report_mch_info();
189  report_pch_info();
190  report_igd_info();
191 }
cpu_type
Definition: cpu.h:347
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define printk(level,...)
Definition: stdlib.h:16
uint32_t cpu_get_feature_flags_ecx(void)
Definition: cpu_common.c:72
uint32_t cpu_get_cpuid(void)
Definition: cpu_common.c:63
#define CPUID_ICELAKE_B0
Definition: cpu_ids.h:40
#define CPUID_ICELAKE_A0
Definition: cpu_ids.h:39
#define CPUID_AES
Definition: msr.h:28
#define CPUID_VMX
Definition: msr.h:24
#define CPUID_SMX
Definition: msr.h:25
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
Definition: pci_ops.h:52
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
Definition: pci_ops.h:46
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
uint32_t get_current_microcode_rev(void)
Definition: microcode.c:112
void report_platform_info(void)
#define PCI_DEVICE_ID
Definition: pci_def.h:9
#define PCI_REVISION_ID
Definition: pci_def.h:41
#define PCI_DID_INTEL_ICL_GT2_ULT_1
Definition: pci_ids.h:3873
#define PCI_DID_INTEL_ICL_BASE_Y_ESPI
Definition: pci_ids.h:2912
#define PCI_DID_INTEL_ICL_SUPER_Y_ESPI
Definition: pci_ids.h:2915
#define PCI_DID_INTEL_ICL_GT3_ULT
Definition: pci_ids.h:3883
#define PCI_DID_INTEL_ICL_ID_Y_2
Definition: pci_ids.h:4004
#define PCI_DID_INTEL_ICL_U_SUPER_U_ESPI_REV0
Definition: pci_ids.h:2910
#define PCI_DID_INTEL_ICL_GT2_ULX_3
Definition: pci_ids.h:3876
#define PCI_DID_INTEL_ICL_GT2_ULT_4
Definition: pci_ids.h:3879
#define PCI_DID_INTEL_ICL_GT2_ULT_5
Definition: pci_ids.h:3881
#define PCI_DID_INTEL_ICL_ID_U_2_2
Definition: pci_ids.h:4002
#define PCI_DID_INTEL_ICL_BASE_U_ESPI
Definition: pci_ids.h:2913
#define PCI_DID_INTEL_ICL_GT2_ULX_0
Definition: pci_ids.h:3871
#define PCI_DID_INTEL_ICL_ID_U
Definition: pci_ids.h:4001
#define PCI_DID_INTEL_ICL_GT2_ULX_4
Definition: pci_ids.h:3878
#define PCI_DID_INTEL_ICL_Y_PREMIUM_ESPI
Definition: pci_ids.h:2914
#define PCI_DID_INTEL_ICL_ID_Y
Definition: pci_ids.h:4003
#define PCI_DID_INTEL_ICL_GT2_ULX_2
Definition: pci_ids.h:3874
#define PCI_DID_INTEL_ICL_GT2_ULT_2
Definition: pci_ids.h:3875
#define PCI_DID_INTEL_ICL_GT0_ULT
Definition: pci_ids.h:3868
#define PCI_DID_INTEL_ICL_GT2_ULX_1
Definition: pci_ids.h:3872
#define PCI_DID_INTEL_ICL_GT1_ULT
Definition: pci_ids.h:3870
#define PCI_DID_INTEL_ICL_U_PREMIUM_ESPI
Definition: pci_ids.h:2911
#define PCI_DID_INTEL_ICL_GT2_ULX_5
Definition: pci_ids.h:3880
#define PCI_DID_INTEL_ICL_U_SUPER_U_ESPI
Definition: pci_ids.h:2909
#define PCI_DID_INTEL_ICL_GT0_5_ULT
Definition: pci_ids.h:3869
#define PCI_DID_INTEL_ICL_GT2_ULT_3
Definition: pci_ids.h:3877
u32 pci_devfn_t
Definition: pci_type.h:8
u16 mchid
u16 igdid
const char * name
u32 cpuid
u16 espiid
unsigned int cpu_id
Definition: chip.h:47
#define PCH_DEV_ESPI
Definition: pci_devs.h:223
#define SA_DEV_IGD
Definition: pci_devs.h:33
u16 pch_type(void)
Definition: pch.c:20
#define SA_DEV_ROOT
Definition: pci_devs.h:26
static void report_igd_info(void)
static struct @573 cpu_table[]
static struct @576 igd_table[]
static void report_mch_info(void)
static uint16_t get_dev_id(pci_devfn_t dev)
static void report_pch_info(void)
static struct @575 pch_table[]
static struct @574 mch_table[]
static void report_cpu_info(void)
static uint8_t get_dev_revision(pci_devfn_t dev)
unsigned short uint16_t
Definition: stdint.h:11
uint32_t u32
Definition: stdint.h:51
uint16_t u16
Definition: stdint.h:48
unsigned char uint8_t
Definition: stdint.h:8
size_t strlen(const char *src)
Definition: string.c:42
uint32_t ecx
Definition: cpu.h:32
uint32_t ebx
Definition: cpu.h:31
uint32_t edx
Definition: cpu.h:33
uint32_t eax
Definition: cpu.h:30