#include <console/console.h>
#include <device/mmio.h>
#include <delay.h>
#include <stddef.h>
#include <timer.h>
#include <soc/addressmap.h>
#include <soc/infracfg.h>
#include <soc/mcucfg.h>
#include <soc/pll.h>

Include dependency graph for pll.c:

Data Structures
struct	mux_sel

struct	rate

Macros
#define	MUX(_id, _reg, _mux_shift, _mux_width)

#define	MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)

Enumerations
enum	mux_id { TOP_AXI_SEL , TOP_MEM_SEL , TOP_DDRPHYCFG_SEL , TOP_MM_SEL , TOP_PWM_SEL , TOP_VDEC_SEL , TOP_VENC_SEL , TOP_MFG_SEL , TOP_CAMTG_SEL , TOP_UART_SEL , TOP_SPI_SEL , TOP_USB20_SEL , TOP_USB30_SEL , TOP_MSDC50_0_H_SEL , TOP_MSDC50_0_SEL , TOP_MSDC30_1_SEL , TOP_MSDC30_2_SEL , TOP_MSDC30_3_SEL , TOP_AUDIO_SEL , TOP_AUD_INTBUS_SEL , TOP_PMICSPI_SEL , TOP_SCP_SEL , TOP_ATB_SEL , TOP_VENC_LT_SEL , TOP_DPI0_SEL , TOP_IRDA_SEL , TOP_CCI400_SEL , TOP_AUD_1_SEL , TOP_AUD_2_SEL , TOP_MEM_MFG_IN_SEL , TOP_AXI_MFG_IN_SEL , TOP_SCAM_SEL , TOP_SPINFI_IFR_SEL , TOP_HDMI_SEL , TOP_DPILVDS_SEL , TOP_MSDC50_2_H_SEL , TOP_HDCP_SEL , TOP_HDCP_24M_SEL , TOP_RTC_SEL , TOP_NR_MUX , TOP_AXI_SEL = 0 , TOP_MM_SEL , TOP_IMG_SEL , TOP_CAM_SEL , TOP_DSP_SEL , TOP_DSP1_SEL , TOP_DSP2_SEL , TOP_IPU_IF_SEL , TOP_MFG_SEL , TOP_MFG_52M_SEL , TOP_CAMTG_SEL , TOP_CAMTG2_SEL , TOP_CAMTG3_SEL , TOP_CAMTG4_SEL , TOP_UART_SEL , TOP_SPI_SEL , TOP_MSDC50_0_HCLK_SEL , TOP_MSDC50_0_SEL , TOP_MSDC30_1_SEL , TOP_MSDC30_2_SEL , TOP_AUDIO_SEL , TOP_AUD_INTBUS_SEL , TOP_PMICSPI_SEL , TOP_PWRAP_ULPOSC_SEL , TOP_ATB_SEL , TOP_PWRMCU_SEL , TOP_DPI0_SEL , TOP_SCAM_SEL , TOP_DISP_PWM_SEL , TOP_USB_TOP_SEL , TOP_SSUSB_XHCI_SEL , TOP_SPM_SEL , TOP_I2C_SEL , TOP_SCP_SEL , TOP_SENINF_SEL , TOP_DXCC_SEL , TOP_AUD_ENGEN1_SEL , TOP_AUD_ENGEN2_SEL , TOP_AES_UFSFDE_SEL , TOP_UFS_SEL , TOP_AUD_1_SEL , TOP_AUD_2_SEL , TOP_NR_MUX , TOP_AXI_SEL , TOP_SCP_SEL , TOP_MFG_SEL , TOP_CAMTG_SEL , TOP_CAMTG1_SEL , TOP_CAMTG2_SEL , TOP_CAMTG3_SEL , TOP_CAMTG4_SEL , TOP_CAMTG5_SEL , TOP_CAMTG6_SEL , TOP_UART_SEL , TOP_SPI_SEL , TOP_MSDC50_0_HCLK_SEL , TOP_MSDC50_0_SEL , TOP_MSDC30_1_SEL , TOP_AUDIO_SEL , TOP_AUD_INTBUS_SEL , TOP_AUD_1_SEL , TOP_AUD_2_SEL , TOP_AUD_ENGEN1_SEL , TOP_AUD_ENGEN2_SEL , TOP_DISP_PWM_SEL , TOP_SSPM_SEL , TOP_DXCC_SEL , TOP_USB_TOP_SEL , TOP_SRCK_SEL , TOP_SPM_SEL , TOP_I2C_SEL , TOP_PWM_SEL , TOP_SENINF_SEL , TOP_SENINF1_SEL , TOP_SENINF2_SEL , TOP_SENINF3_SEL , TOP_AES_MSDCFDE_SEL , TOP_PWRAP_ULPOSC_SEL , TOP_CAMTM_SEL , TOP_VENC_SEL , TOP_CAM_SEL , TOP_IMG1_SEL , TOP_IPE_SEL , TOP_DPMAIF_SEL , TOP_VDEC_SEL , TOP_DISP_SEL , TOP_MDP_SEL , TOP_AUDIO_H_SEL , TOP_UFS_SEL , TOP_AES_FDE_SEL , TOP_AUDIODSP_SEL , TOP_DVFSRC_SEL , TOP_DSI_OCC_SEL , TOP_SPMI_MST_SEL , TOP_SPINOR_SEL , TOP_NNA_SEL , TOP_NNA1_SEL , TOP_NNA2_SEL , TOP_SSUSB_XHCI_SEL , TOP_SSUSB_TOP_1P_SEL , TOP_SSUSB_XHCI_1P_SEL , TOP_WPE_SEL , TOP_MEM_SEL , TOP_DPI_SEL , TOP_U3_OCC_250M_SEL , TOP_U3_OCC_500M_SEL , TOP_ADSP_BUS_SEL , TOP_NR_MUX , TOP_AXI_SEL , TOP_SPM_SEL , TOP_SCP_SEL , TOP_BUS_AXIMEM_SEL , TOP_DISP_SEL , TOP_MDP_SEL , TOP_IMG1_SEL , TOP_IMG2_SEL , TOP_IPE_SEL , TOP_DPE_SEL , TOP_CAM_SEL , TOP_CCU_SEL , TOP_DSP_SEL , TOP_DSP7_SEL , TOP_MFG_REF_SEL , TOP_MFG_PLL_SEL , TOP_CAMTG_SEL , TOP_CAMTG2_SEL , TOP_CAMTG3_SEL , TOP_CAMTG4_SEL , TOP_CAMTG5_SEL , TOP_CAMTG6_SEL , TOP_UART_SEL , TOP_SPI_SEL , TOP_MSDC50_0_HCLK_SEL , TOP_MSDC50_0_SEL , TOP_MSDC30_1_SEL , TOP_MSDC30_2_SEL , TOP_AUDIO_SEL , TOP_AUD_INTBUS_SEL , TOP_PWRAP_ULPOSC_SEL , TOP_ATB_SEL , TOP_PWRMCU_SEL , TOP_DPI_SEL , TOP_SCAM_SEL , TOP_DISP_PWM_SEL , TOP_USB_TOP_SEL , TOP_SSUSB_XHCI_SEL , TOP_I2C_SEL , TOP_SENINF_SEL , TOP_SENINF1_SEL , TOP_SENINF2_SEL , TOP_SENINF3_SEL , TOP_TL_SEL , TOP_DXCC_SEL , TOP_AUD_ENGEN1_SEL , TOP_AUD_ENGEN2_SEL , TOP_AES_UFSFDE_SEL , TOP_UFS_SEL , TOP_AUD_1_SEL , TOP_AUD_2_SEL , TOP_ADSP_SEL , TOP_DPMAIF_MAIN_SEL , TOP_VENC_SEL , TOP_VDEC_SEL , TOP_CAMTM_SEL , TOP_PWM_SEL , TOP_AUDIO_H_SEL , TOP_SPMI_MST_SEL , TOP_DVFSRC_SEL , TOP_AES_MSDCFDE_SEL , TOP_MCUPM_SEL , TOP_SFLASH_SEL , TOP_NR_MUX , TOP_AXI_SEL , TOP_SPM_SEL , TOP_SCP_SEL , TOP_BUS_AXIMEM_SEL , TOP_VPP_SEL , TOP_ETHDR_SEL , TOP_IPE_SEL , TOP_CAM_SEL , TOP_CCU_SEL , TOP_IMG_SEL , TOP_CAMTM_SEL , TOP_DSP_SEL , TOP_DSP1_SEL , TOP_DSP2_SEL , TOP_DSP3_SEL , TOP_DSP4_SEL , TOP_DSP5_SEL , TOP_DSP6_SEL , TOP_DSP7_SEL , TOP_IPU_IF_SEL , TOP_MFG_SEL , TOP_CAMTG_SEL , TOP_CAMTG2_SEL , TOP_CAMTG3_SEL , TOP_CAMTG4_SEL , TOP_CAMTG5_SEL , TOP_UART_SEL , TOP_SPI_SEL , TOP_SPIS_SEL , TOP_MSDC50_0_H_SEL , TOP_MSDC50_0_SEL , TOP_MSDC30_1_SEL , TOP_MSDC30_2_SEL , TOP_INTDIR_SEL , TOP_AUD_INTBUS_SEL , TOP_AUDIO_H_SEL , TOP_PWRAP_ULPOSC_SEL , TOP_ATB_SEL , TOP_PWRMCU_SEL , TOP_DP_SEL , TOP_EDP_SEL , TOP_DPI_SEL , TOP_DISP_PWM0_SEL , TOP_DISP_PWM1_SEL , TOP_USB_SEL , TOP_SSUSB_XHCI_SEL , TOP_USB_1P_SEL , TOP_SSUSB_XHCI_1P_SEL , TOP_USB_2P_SEL , TOP_SSUSB_XHCI_2P_SEL , TOP_USB_3P_SEL , TOP_SSUSB_XHCI_3P_SEL , TOP_I2C_SEL , TOP_SENINF_SEL , TOP_SENINF1_SEL , TOP_SENINF2_SEL , TOP_SENINF3_SEL , TOP_GCPU_SEL , TOP_DXCC_SEL , TOP_DPMAIF_SEL , TOP_AES_UFSFDE_SEL , TOP_UFS_SEL , TOP_UFS_TICK1US_SEL , TOP_UFS_MP_SAP_SEL , TOP_VENC_SEL , TOP_VDEC_SEL , TOP_PWM_SEL , TOP_MCUPM_SEL , TOP_SPMI_P_MST_SEL , TOP_SPMI_M_MST_SEL , TOP_DVFSRC_SEL , TOP_TL_SEL , TOP_TL_P1_SEL , TOP_AES_MSDCFDE_SEL , TOP_DSI_OCC_SEL , TOP_WPE_VPP_SEL , TOP_HDCP_SEL , TOP_HDCP_24M_SEL , TOP_HD20_DACR_REF_SEL , TOP_HD20_HDCP_C_SEL , TOP_HDMI_XTAL_SEL , TOP_HDMI_APB_SEL , TOP_SNPS_ETH_250M_SEL , TOP_SNPS_ETH_62P4M_PTP_SEL , TOP_SNPS_ETH_50M_RMII_SEL , TOP_DGI_OUT_SEL , TOP_NNA0_SEL , TOP_NNA1_SEL , TOP_ADSP_SEL , TOP_ASM_H_SEL , TOP_ASM_M_SEL , TOP_ASM_L_SEL , TOP_APLL1_SEL , TOP_APLL2_SEL , TOP_APLL3_SEL , TOP_APLL4_SEL , TOP_APLL5_SEL , TOP_I2SO1_M_SEL , TOP_I2SO2_M_SEL , TOP_I2SI1_M_SEL , TOP_I2SI2_M_SEL , TOP_DPTX_M_SEL , TOP_AUD_IEC_SEL , TOP_A1SYS_HP_SEL , TOP_A2SYS_SEL , TOP_A3SYS_SEL , TOP_A4SYS_SEL , TOP_SPINFI_B_SEL , TOP_NFI1X_SEL , TOP_ECC_SEL , TOP_AUDIO_LOCAL_BUS_SEL , TOP_SPINOR_SEL , TOP_DVIO_DGI_REF_SEL , TOP_SRCK_SEL , TOP_RSVD1_SEL , TOP_MFG_FAST_SEL , TOP_NR_MUX }

enum	pll_id { APMIXED_ARMCA15PLL , APMIXED_ARMCA7PLL , APMIXED_MAINPLL , APMIXED_UNIVPLL , APMIXED_MMPLL , APMIXED_MSDCPLL , APMIXED_VENCPLL , APMIXED_TVDPLL , APMIXED_MPLL , APMIXED_VCODECPLL , APMIXED_APLL1 , APMIXED_APLL2 , APMIXED_LVDSPLL , APMIXED_MSDCPLL2 , APMIXED_NR_PLL , APMIXED_ARMPLL_LL , APMIXED_ARMPLL_L , APMIXED_CCIPLL , APMIXED_MAINPLL , APMIXED_UNIVPLL , APMIXED_MSDCPLL , APMIXED_MMPLL , APMIXED_MFGPLL , APMIXED_TVDPLL , APMIXED_APLL1 , APMIXED_APLL2 , APMIXED_MPLL , APMIXED_PLL_MAX , APMIXED_ARMPLL_LL , APMIXED_ARMPLL_BL , APMIXED_CCIPLL , APMIXED_MAINPLL , APMIXED_UNIV2PLL , APMIXED_MSDCPLL , APMIXED_MMPLL , APMIXED_NNAPLL , APMIXED_NNA2PLL , APMIXED_ADSPPLL , APMIXED_MFGPLL , APMIXED_TVDPLL , APMIXED_APLL1 , APMIXED_APLL2 , APMIXED_PLL_MAX , APMIXED_ARMPLL_LL , APMIXED_ARMPLL_BL , APMIXED_CCIPLL , APMIXED_MAINPLL , APMIXED_UNIVPLL , APMIXED_USBPLL , APMIXED_MSDCPLL , APMIXED_MMPLL , APMIXED_ADSPPLL , APMIXED_MFGPLL , APMIXED_TVDPLL , APMIXED_APLL1 , APMIXED_APLL2 , APMIXED_PLL_MAX , APMIXED_ARMPLL_LL , APMIXED_ARMPLL_BL , APMIXED_CCIPLL , APMIXED_NNAPLL , APMIXED_RESPLL , APMIXED_ETHPLL , APMIXED_MSDCPLL , APMIXED_TVDPLL1 , APMIXED_TVDPLL2 , APMIXED_MMPLL , APMIXED_MAINPLL , APMIXED_VDECPLL , APMIXED_IMGPLL , APMIXED_UNIVPLL , APMIXED_HDMIPLL1 , APMIXED_HDMIPLL2 , APMIXED_HDMIRX_APLL , APMIXED_USB1PLL , APMIXED_ADSPPLL , APMIXED_APLL1 , APMIXED_APLL2 , APMIXED_APLL3 , APMIXED_APLL4 , APMIXED_APLL5 , APMIXED_MFGPLL , APMIXED_DGIPLL , APMIXED_PLL_MAX }

Functions
void	pll_set_pcw_change (const struct pll *pll)

void	mt_pll_init (void)

void	mt_pll_raise_little_cpu_freq (u32 freq)

void	mt_pll_raise_cci_freq (u32 freq)

u32	mt_fmeter_get_freq_khz (enum fmeter_type type, u32 id)

Variables
static const struct mux	muxes []

static const struct mux_sel	mux_sels []

static const u32	pll_div_rate []

static const struct pll	plls []

static const struct rate	rates []

Macro Definition Documentation

◆ MUX

#define MUX	(	_id,
		_reg,
		_mux_shift,
		_mux_width
	)

Value:

        [_id] = {                                       \
                .reg = &mtk_topckgen->_reg,             \
                .mux_shift = _mux_shift,                \
                .mux_width = _mux_width,                \
        }

Definition at line 87 of file pll.c.

◆ MUX_UPD

#define MUX_UPD	(	_id,
		_reg,
		_mux_shift,
		_mux_width,
		_upd_reg,
		_upd_shift
	)

Value:

        [_id] = {                                                       \
                .reg = &mtk_topckgen->_reg,                             \
                .set_reg = &mtk_topckgen->_reg##_set,                   \
                .clr_reg = &mtk_topckgen->_reg##_clr,                   \
                .mux_shift = _mux_shift,                                \
                .mux_width = _mux_width,                                \
                .upd_reg = &mtk_topckgen->_upd_reg,                     \
                .upd_shift = _upd_shift,                                \
        }

Definition at line 94 of file pll.c.

Enumeration Type Documentation

◆ mux_id

enum mux_id

Enumerator
TOP_AXI_SEL
TOP_MEM_SEL
TOP_DDRPHYCFG_SEL
TOP_MM_SEL
TOP_PWM_SEL
TOP_VDEC_SEL
TOP_VENC_SEL
TOP_MFG_SEL
TOP_CAMTG_SEL
TOP_UART_SEL
TOP_SPI_SEL
TOP_USB20_SEL
TOP_USB30_SEL
TOP_MSDC50_0_H_SEL
TOP_MSDC50_0_SEL
TOP_MSDC30_1_SEL
TOP_MSDC30_2_SEL
TOP_MSDC30_3_SEL
TOP_AUDIO_SEL
TOP_AUD_INTBUS_SEL
TOP_PMICSPI_SEL
TOP_SCP_SEL
TOP_ATB_SEL
TOP_VENC_LT_SEL
TOP_DPI0_SEL
TOP_IRDA_SEL
TOP_CCI400_SEL
TOP_AUD_1_SEL
TOP_AUD_2_SEL
TOP_MEM_MFG_IN_SEL
TOP_AXI_MFG_IN_SEL
TOP_SCAM_SEL
TOP_SPINFI_IFR_SEL
TOP_HDMI_SEL
TOP_DPILVDS_SEL
TOP_MSDC50_2_H_SEL
TOP_HDCP_SEL
TOP_HDCP_24M_SEL
TOP_RTC_SEL
TOP_NR_MUX
TOP_AXI_SEL
TOP_MM_SEL
TOP_IMG_SEL
TOP_CAM_SEL
TOP_DSP_SEL
TOP_DSP1_SEL
TOP_DSP2_SEL
TOP_IPU_IF_SEL
TOP_MFG_SEL
TOP_MFG_52M_SEL
TOP_CAMTG_SEL
TOP_CAMTG2_SEL
TOP_CAMTG3_SEL
TOP_CAMTG4_SEL
TOP_UART_SEL
TOP_SPI_SEL
TOP_MSDC50_0_HCLK_SEL
TOP_MSDC50_0_SEL
TOP_MSDC30_1_SEL
TOP_MSDC30_2_SEL
TOP_AUDIO_SEL
TOP_AUD_INTBUS_SEL
TOP_PMICSPI_SEL
TOP_PWRAP_ULPOSC_SEL
TOP_ATB_SEL
TOP_PWRMCU_SEL
TOP_DPI0_SEL
TOP_SCAM_SEL
TOP_DISP_PWM_SEL
TOP_USB_TOP_SEL
TOP_SSUSB_XHCI_SEL
TOP_SPM_SEL
TOP_I2C_SEL
TOP_SCP_SEL
TOP_SENINF_SEL
TOP_DXCC_SEL
TOP_AUD_ENGEN1_SEL
TOP_AUD_ENGEN2_SEL
TOP_AES_UFSFDE_SEL
TOP_UFS_SEL
TOP_AUD_1_SEL
TOP_AUD_2_SEL
TOP_NR_MUX
TOP_AXI_SEL
TOP_SCP_SEL
TOP_MFG_SEL
TOP_CAMTG_SEL
TOP_CAMTG1_SEL
TOP_CAMTG2_SEL
TOP_CAMTG3_SEL
TOP_CAMTG4_SEL
TOP_CAMTG5_SEL
TOP_CAMTG6_SEL
TOP_UART_SEL
TOP_SPI_SEL
TOP_MSDC50_0_HCLK_SEL
TOP_MSDC50_0_SEL
TOP_MSDC30_1_SEL
TOP_AUDIO_SEL
TOP_AUD_INTBUS_SEL
TOP_AUD_1_SEL
TOP_AUD_2_SEL
TOP_AUD_ENGEN1_SEL
TOP_AUD_ENGEN2_SEL
TOP_DISP_PWM_SEL
TOP_SSPM_SEL
TOP_DXCC_SEL
TOP_USB_TOP_SEL
TOP_SRCK_SEL
TOP_SPM_SEL
TOP_I2C_SEL
TOP_PWM_SEL
TOP_SENINF_SEL
TOP_SENINF1_SEL
TOP_SENINF2_SEL
TOP_SENINF3_SEL
TOP_AES_MSDCFDE_SEL
TOP_PWRAP_ULPOSC_SEL
TOP_CAMTM_SEL
TOP_VENC_SEL
TOP_CAM_SEL
TOP_IMG1_SEL
TOP_IPE_SEL
TOP_DPMAIF_SEL
TOP_VDEC_SEL
TOP_DISP_SEL
TOP_MDP_SEL
TOP_AUDIO_H_SEL
TOP_UFS_SEL
TOP_AES_FDE_SEL
TOP_AUDIODSP_SEL
TOP_DVFSRC_SEL
TOP_DSI_OCC_SEL
TOP_SPMI_MST_SEL
TOP_SPINOR_SEL
TOP_NNA_SEL
TOP_NNA1_SEL
TOP_NNA2_SEL
TOP_SSUSB_XHCI_SEL
TOP_SSUSB_TOP_1P_SEL
TOP_SSUSB_XHCI_1P_SEL
TOP_WPE_SEL
TOP_MEM_SEL
TOP_DPI_SEL
TOP_U3_OCC_250M_SEL
TOP_U3_OCC_500M_SEL
TOP_ADSP_BUS_SEL
TOP_NR_MUX
TOP_AXI_SEL
TOP_SPM_SEL
TOP_SCP_SEL
TOP_BUS_AXIMEM_SEL
TOP_DISP_SEL
TOP_MDP_SEL
TOP_IMG1_SEL
TOP_IMG2_SEL
TOP_IPE_SEL
TOP_DPE_SEL
TOP_CAM_SEL
TOP_CCU_SEL
TOP_DSP_SEL
TOP_DSP7_SEL
TOP_MFG_REF_SEL
TOP_MFG_PLL_SEL
TOP_CAMTG_SEL
TOP_CAMTG2_SEL
TOP_CAMTG3_SEL
TOP_CAMTG4_SEL
TOP_CAMTG5_SEL
TOP_CAMTG6_SEL
TOP_UART_SEL
TOP_SPI_SEL
TOP_MSDC50_0_HCLK_SEL
TOP_MSDC50_0_SEL
TOP_MSDC30_1_SEL
TOP_MSDC30_2_SEL
TOP_AUDIO_SEL
TOP_AUD_INTBUS_SEL
TOP_PWRAP_ULPOSC_SEL
TOP_ATB_SEL
TOP_PWRMCU_SEL
TOP_DPI_SEL
TOP_SCAM_SEL
TOP_DISP_PWM_SEL
TOP_USB_TOP_SEL
TOP_SSUSB_XHCI_SEL
TOP_I2C_SEL
TOP_SENINF_SEL
TOP_SENINF1_SEL
TOP_SENINF2_SEL
TOP_SENINF3_SEL
TOP_TL_SEL
TOP_DXCC_SEL
TOP_AUD_ENGEN1_SEL
TOP_AUD_ENGEN2_SEL
TOP_AES_UFSFDE_SEL
TOP_UFS_SEL
TOP_AUD_1_SEL
TOP_AUD_2_SEL
TOP_ADSP_SEL
TOP_DPMAIF_MAIN_SEL
TOP_VENC_SEL
TOP_VDEC_SEL
TOP_CAMTM_SEL
TOP_PWM_SEL
TOP_AUDIO_H_SEL
TOP_SPMI_MST_SEL
TOP_DVFSRC_SEL
TOP_AES_MSDCFDE_SEL
TOP_MCUPM_SEL
TOP_SFLASH_SEL
TOP_NR_MUX
TOP_AXI_SEL
TOP_SPM_SEL
TOP_SCP_SEL
TOP_BUS_AXIMEM_SEL
TOP_VPP_SEL
TOP_ETHDR_SEL
TOP_IPE_SEL
TOP_CAM_SEL
TOP_CCU_SEL
TOP_IMG_SEL
TOP_CAMTM_SEL
TOP_DSP_SEL
TOP_DSP1_SEL
TOP_DSP2_SEL
TOP_DSP3_SEL
TOP_DSP4_SEL
TOP_DSP5_SEL
TOP_DSP6_SEL
TOP_DSP7_SEL
TOP_IPU_IF_SEL
TOP_MFG_SEL
TOP_CAMTG_SEL
TOP_CAMTG2_SEL
TOP_CAMTG3_SEL
TOP_CAMTG4_SEL
TOP_CAMTG5_SEL
TOP_UART_SEL
TOP_SPI_SEL
TOP_SPIS_SEL
TOP_MSDC50_0_H_SEL
TOP_MSDC50_0_SEL
TOP_MSDC30_1_SEL
TOP_MSDC30_2_SEL
TOP_INTDIR_SEL
TOP_AUD_INTBUS_SEL
TOP_AUDIO_H_SEL
TOP_PWRAP_ULPOSC_SEL
TOP_ATB_SEL
TOP_PWRMCU_SEL
TOP_DP_SEL
TOP_EDP_SEL
TOP_DPI_SEL
TOP_DISP_PWM0_SEL
TOP_DISP_PWM1_SEL
TOP_USB_SEL
TOP_SSUSB_XHCI_SEL
TOP_USB_1P_SEL
TOP_SSUSB_XHCI_1P_SEL
TOP_USB_2P_SEL
TOP_SSUSB_XHCI_2P_SEL
TOP_USB_3P_SEL
TOP_SSUSB_XHCI_3P_SEL
TOP_I2C_SEL
TOP_SENINF_SEL
TOP_SENINF1_SEL
TOP_SENINF2_SEL
TOP_SENINF3_SEL
TOP_GCPU_SEL
TOP_DXCC_SEL
TOP_DPMAIF_SEL
TOP_AES_UFSFDE_SEL
TOP_UFS_SEL
TOP_UFS_TICK1US_SEL
TOP_UFS_MP_SAP_SEL
TOP_VENC_SEL
TOP_VDEC_SEL
TOP_PWM_SEL
TOP_MCUPM_SEL
TOP_SPMI_P_MST_SEL
TOP_SPMI_M_MST_SEL
TOP_DVFSRC_SEL
TOP_TL_SEL
TOP_TL_P1_SEL
TOP_AES_MSDCFDE_SEL
TOP_DSI_OCC_SEL
TOP_WPE_VPP_SEL
TOP_HDCP_SEL
TOP_HDCP_24M_SEL
TOP_HD20_DACR_REF_SEL
TOP_HD20_HDCP_C_SEL
TOP_HDMI_XTAL_SEL
TOP_HDMI_APB_SEL
TOP_SNPS_ETH_250M_SEL
TOP_SNPS_ETH_62P4M_PTP_SEL
TOP_SNPS_ETH_50M_RMII_SEL
TOP_DGI_OUT_SEL
TOP_NNA0_SEL
TOP_NNA1_SEL
TOP_ADSP_SEL
TOP_ASM_H_SEL
TOP_ASM_M_SEL
TOP_ASM_L_SEL
TOP_APLL1_SEL
TOP_APLL2_SEL
TOP_APLL3_SEL
TOP_APLL4_SEL
TOP_APLL5_SEL
TOP_I2SO1_M_SEL
TOP_I2SO2_M_SEL
TOP_I2SI1_M_SEL
TOP_I2SI2_M_SEL
TOP_DPTX_M_SEL
TOP_AUD_IEC_SEL
TOP_A1SYS_HP_SEL
TOP_A2SYS_SEL
TOP_A3SYS_SEL
TOP_A4SYS_SEL
TOP_SPINFI_B_SEL
TOP_NFI1X_SEL
TOP_ECC_SEL
TOP_AUDIO_LOCAL_BUS_SEL
TOP_SPINOR_SEL
TOP_DVIO_DGI_REF_SEL
TOP_SRCK_SEL
TOP_RSVD1_SEL
TOP_MFG_FAST_SEL
TOP_NR_MUX

Definition at line 19 of file pll.c.

◆ pll_id

enum pll_id

Enumerator
APMIXED_ARMCA15PLL
APMIXED_ARMCA7PLL
APMIXED_MAINPLL
APMIXED_UNIVPLL
APMIXED_MMPLL
APMIXED_MSDCPLL
APMIXED_VENCPLL
APMIXED_TVDPLL
APMIXED_MPLL
APMIXED_VCODECPLL
APMIXED_APLL1
APMIXED_APLL2
APMIXED_LVDSPLL
APMIXED_MSDCPLL2
APMIXED_NR_PLL
APMIXED_ARMPLL_LL
APMIXED_ARMPLL_L
APMIXED_CCIPLL
APMIXED_MAINPLL
APMIXED_UNIVPLL
APMIXED_MSDCPLL
APMIXED_MMPLL
APMIXED_MFGPLL
APMIXED_TVDPLL
APMIXED_APLL1
APMIXED_APLL2
APMIXED_MPLL
APMIXED_PLL_MAX
APMIXED_ARMPLL_LL
APMIXED_ARMPLL_BL
APMIXED_CCIPLL
APMIXED_MAINPLL
APMIXED_UNIV2PLL
APMIXED_MSDCPLL
APMIXED_MMPLL
APMIXED_NNAPLL
APMIXED_NNA2PLL
APMIXED_ADSPPLL
APMIXED_MFGPLL
APMIXED_TVDPLL
APMIXED_APLL1
APMIXED_APLL2
APMIXED_PLL_MAX
APMIXED_ARMPLL_LL
APMIXED_ARMPLL_BL
APMIXED_CCIPLL
APMIXED_MAINPLL
APMIXED_UNIVPLL
APMIXED_USBPLL
APMIXED_MSDCPLL
APMIXED_MMPLL
APMIXED_ADSPPLL
APMIXED_MFGPLL
APMIXED_TVDPLL
APMIXED_APLL1
APMIXED_APLL2
APMIXED_PLL_MAX
APMIXED_ARMPLL_LL
APMIXED_ARMPLL_BL
APMIXED_CCIPLL
APMIXED_NNAPLL
APMIXED_RESPLL
APMIXED_ETHPLL
APMIXED_MSDCPLL
APMIXED_TVDPLL1
APMIXED_TVDPLL2
APMIXED_MMPLL
APMIXED_MAINPLL
APMIXED_VDECPLL
APMIXED_IMGPLL
APMIXED_UNIVPLL
APMIXED_HDMIPLL1
APMIXED_HDMIPLL2
APMIXED_HDMIRX_APLL
APMIXED_USB1PLL
APMIXED_ADSPPLL
APMIXED_APLL1
APMIXED_APLL2
APMIXED_APLL3
APMIXED_APLL4
APMIXED_APLL5
APMIXED_MFGPLL
APMIXED_DGIPLL
APMIXED_PLL_MAX

Definition at line 272 of file pll.c.

Function Documentation

◆ mt_fmeter_get_freq_khz()

u32 mt_fmeter_get_freq_khz	(	enum fmeter_type	type,
		u32	id
	)

Definition at line 519 of file pll.c.

◆ mt_pll_init()

void mt_pll_init ( void )

Definition at line 371 of file pll.c.

References APMIXED_PLL_MAX, ARMPLL_DIVIDER_PLL1_EN, ARMPLL_DIVIDER_PLL2_EN, ARRAY_SIZE, BIT, mt8186_mcucfg_regs::bus_plldiv_cfg, clrbits32, clrsetbits32, mt8186_mcucfg_regs::cpu_plldiv_cfg0, mt8186_mcucfg_regs::cpu_plldiv_cfg1, GLITCH_FREE_EN, mt8186_infracfg_ao_regs::infra_bus_dcm_ctrl, MCU_DIV_1, MCU_DIV_MASK, MCU_MUX_MASK, MCU_MUX_SRC_PLL, MHz, mt8186_infracfg_ao_regs::module_sw_cg_0_clr, mt8186_infracfg_ao_regs::module_sw_cg_1_clr, mt8186_infracfg_ao_regs::module_sw_cg_3_clr, mt8186_infracfg_ao, MT8186_PLL_EN, mtk_apmixed, mtk_mcucfg, mtk_topckgen, mux_sels, mux_set_sel(), muxes, NO_RSTB_SHIFT, mt8186_infracfg_ao_regs::p2p_rx_clk_on, mt8186_infracfg_ao_regs::peri_bus_dcm_ctrl, PLL_CKSQ_ON_DELAY, PLL_DIV_EN, PLL_EN_DELAY, PLL_ISO, PLL_ISO_DELAY, PLL_PWR_ON, PLL_PWR_ON_DELAY, pll_set_rate(), plls, rates, read32(), SET32_BITFIELDS, setbits32, udelay(), and write32().

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◆ mt_pll_raise_cci_freq()

void mt_pll_raise_cci_freq ( u32 freq )

Definition at line 500 of file pll.c.

◆ mt_pll_raise_little_cpu_freq()

void mt_pll_raise_little_cpu_freq ( u32 freq )

Definition at line 481 of file pll.c.

References APMIXED_ARMPLL_LL, clrbits32, clrsetbits32, mt8186_mcucfg_regs::cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M, MCU_MUX_SRC_PLL, MT8186_PLL_EN, mtk_mcucfg, PLL_EN_DELAY, pll_set_rate(), plls, setbits32, and udelay().

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◆ pll_set_pcw_change()

void pll_set_pcw_change ( const struct pll * pll )

Definition at line 366 of file pll.c.

References pll::div_reg, PLL_PCW_CHG, and setbits32.

Variable Documentation

◆ mux_sels

const struct mux_sel mux_sels[]

static

Definition at line 1 of file pll.c.

Referenced by mt_pll_init().

◆ muxes

const struct mux muxes[]

static

Definition at line 1 of file pll.c.

Referenced by mt_pll_init().

◆ pll_div_rate

const u32 pll_div_rate[]

static

Initial value:

= {
        3800UL * MHz,
        1900 * MHz,
        950 * MHz,
        475 * MHz,
        237500 * KHz,
        0,
}

Definition at line 290 of file pll.c.

◆ plls

const struct pll plls[]

static

Definition at line 290 of file pll.c.

Referenced by mt_pll_init(), mt_pll_raise_cci_freq(), and mt_pll_raise_little_cpu_freq().

◆ rates

const struct rate rates[]

static

Initial value:

= {
        { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ },
        { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ },
        { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ },
        { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ },
        { .id = APMIXED_UNIV2PLL, .rate = UNIV2PLL_HZ },
        { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ },
        { .id = APMIXED_MMPLL, .rate = MMPLL_HZ },
        { .id = APMIXED_NNAPLL, .rate = NNAPLL_HZ },
        { .id = APMIXED_NNA2PLL, .rate = NNA2PLL_HZ },
        { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ },
        { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ },
        { .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ },
        { .id = APMIXED_APLL1, .rate = APLL1_HZ },
        { .id = APMIXED_APLL2, .rate = APLL2_HZ },
}

Definition at line 290 of file pll.c.

Referenced by mt_pll_init().

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ MUX

◆ MUX_UPD

Enumeration Type Documentation

◆ mux_id

◆ pll_id

Function Documentation

◆ mt_fmeter_get_freq_khz()

◆ mt_pll_init()

◆ mt_pll_raise_cci_freq()

◆ mt_pll_raise_little_cpu_freq()

◆ pll_set_pcw_change()

Variable Documentation

◆ mux_sels

◆ muxes

◆ pll_div_rate

◆ plls

◆ rates