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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <console/console.h>
#include <device/mmio.h>
#include <delay.h>
#include <stddef.h>
#include <timer.h>
#include <soc/addressmap.h>
#include <soc/infracfg.h>
#include <soc/mcucfg.h>
#include <soc/pll.h>
#include <soc/wdt.h>
Go to the source code of this file.
Data Structures | |
struct | mux_sel |
struct | rate |
Macros | |
#define | MUX(_id, _reg, _mux_shift, _mux_width) |
#define | MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift) |
Functions | |
void | pll_set_pcw_change (const struct pll *pll) |
void | mt_pll_init (void) |
void | mt_pll_raise_little_cpu_freq (u32 freq) |
u32 | mt_fmeter_get_freq_khz (enum fmeter_type type, u32 id) |
void | mt_pll_raise_cci_freq (u32 freq) |
Variables | |
static const struct mux | muxes [] |
static const struct mux_sel | mux_sels [] |
const u32 | pll_div_rate [] |
static const struct pll | plls [] |
static const struct rate | rates [] |
#define MUX | ( | _id, | |
_reg, | |||
_mux_shift, | |||
_mux_width | |||
) |
#define MUX_UPD | ( | _id, | |
_reg, | |||
_mux_shift, | |||
_mux_width, | |||
_upd_reg, | |||
_upd_shift | |||
) |
enum mux_id |
enum pll_id |
u32 mt_fmeter_get_freq_khz | ( | enum fmeter_type | type, |
u32 | id | ||
) |
Definition at line 503 of file pll.c.
References BIOS_WARNING, count, die(), FMETER_ABIST, FMETER_CKGEN, mtk_topckgen, printk, read32(), READ32_BITFIELD, SET32_BITFIELDS, type, wait_us, and write32().
Definition at line 369 of file pll.c.
References APMIXED_PLL_MAX, APMIXED_USBPLL, ARRAY_SIZE, mt8186_mcucfg_regs::bus_plldiv_cfg, clrbits32, clrsetbits32, mt8186_mcucfg_regs::cpu_plldiv_cfg0, mt8186_mcucfg_regs::cpu_plldiv_cfg1, mt8192_infracfg_regs::infra_aximem_idle_bit_en_0, mt8192_infracfg_regs::infra_bus_dcm_ctrl, INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON, INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_BUS_DCM_REG0_ON, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON, INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON, INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, INFRACFG_AO_PERI_BUS_DCM_REG0_ON, INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, INFRACFG_AO_PERI_MODULE_DCM_REG0_ON, MCU_DIV_1, MCU_DIV_MASK, MCU_MUX_MASK, MCU_MUX_SRC_PLL, mt8192_infracfg_regs::module_sw_cg_2_clr, mt8192_infracfg_regs::module_sw_cg_2_set, mt8192_infracfg, mtk_apmixed, mtk_mcucfg, mtk_topckgen, mtk_wdt, mux_sels, mux_set_sel(), muxes, NO_RSTB_SHIFT, mt8192_infracfg_regs::p2p_rx_clk_on, mt8192_infracfg_regs::peri_bus_dcm_ctrl, PLL_DIV_EN, PLL_EN, PLL_EN_DELAY, PLL_ISO, PLL_ISO_DELAY, PLL_PWR_ON, PLL_PWR_ON_DELAY, pll_set_rate(), plls, rates, read32(), SET32_BITFIELDS, setbits32, udelay(), USBPLL_EN, mtk_wdt_regs::wdt_swsysrst, and write32().
Definition at line 563 of file pll.c.
References APMIXED_CCIPLL, mt8186_mcucfg_regs::bus_plldiv_cfg, clrbits32, clrsetbits32, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1, MCU_MUX_SRC_PLL, mtk_mcucfg, mtk_topckgen, PLL_EN, PLL_EN_DELAY, pll_set_rate(), plls, setbits32, and udelay().
Definition at line 478 of file pll.c.
References APMIXED_ARMPLL_LL, clrbits32, clrsetbits32, mt8186_mcucfg_regs::cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1, MCU_MUX_SRC_PLL, mtk_mcucfg, mtk_topckgen, PLL_EN, PLL_EN_DELAY, pll_set_rate(), plls, setbits32, and udelay().
Definition at line 364 of file pll.c.
References pll::div_reg, PLL_PCW_CHG, and setbits32.
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Definition at line 1 of file pll.c.
Referenced by mt_pll_init().
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Definition at line 1 of file pll.c.
Referenced by mt_pll_init().
const u32 pll_div_rate[] |
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Definition at line 292 of file pll.c.
Referenced by mt_pll_init(), mt_pll_raise_cci_freq(), and mt_pll_raise_little_cpu_freq().
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static |
Definition at line 292 of file pll.c.
Referenced by mt_pll_init().