coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <stdint.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <acpi/acpi.h>
#include <bootstate.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <drivers/uart/uart8250reg.h>
#include <soc/iomap.h>
#include <soc/irq.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/ramstage.h>
#include <soc/spi.h>
#include "chip.h"
#include <acpi/acpigen.h>
Go to the source code of this file.
Macros | |
#define | LPC_DEFAULT_IO_RANGE_LOWER 0 |
#define | LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
Variables | |
static struct device_operations | device_ops |
static const struct pci_driver southcluster | __pci_driver |
#define LPC_DEFAULT_IO_RANGE_LOWER 0 |
Definition at line 45 of file southcluster.c.
#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
Definition at line 46 of file southcluster.c.
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inlinestatic |
Definition at line 26 of file southcluster.c.
References addr, and mmio_resource.
Referenced by sc_add_mmio_resources().
BOOT_STATE_INIT_ENTRY | ( | BS_OS_RESUME | , |
BS_ON_ENTRY | , | ||
finalize_chipset | , | ||
NULL | |||
) |
BOOT_STATE_INIT_ENTRY | ( | BS_PAYLOAD_LOAD | , |
BS_ON_EXIT | , | ||
finalize_chipset | , | ||
NULL | |||
) |
Definition at line 116 of file southcluster.c.
References outb(), pci_read_config32(), UART8250_DLL, UART8250_DLM, UART8250_FCR, UART8250_FCR_FIFO_EN, UART8250_IER, UART8250_LCR, UART8250_LCR_DLAB, UART8250_MCR, UART8250_MCR_DTR, UART8250_MCR_RTS, and UART_CONT.
Referenced by sc_init().
Definition at line 503 of file southcluster.c.
References BCR, BCR_LE, BILD, BIOS_DEBUG, CF9LOCK, ETR, FLOCKDN, GCS, GEN_PMCON2, HSFSTS, LVSCC, spi_config::lvscc, mainboard_get_spi_config(), spi_config::opmenu, OPMENU0, OPMENU1, OPTYPE, spi_config::optype, PMC_BASE_ADDRESS, PREOP, spi_config::preop, printk, RCBA_BASE_ADDRESS, read16(), read32(), SLPSX_STR_POL_LOCK, SMI_LOCK, SPI_BASE_ADDRESS, UVSCC, spi_config::uvscc, VCL, write16(), and write32().
Definition at line 310 of file southcluster.c.
References PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_COMMAND, PCI_COMMAND_MEMORY, pci_write_config16(), pci_write_config32(), pci_write_config8(), read32(), TEMP_BASE_ADDRESS, and write32().
Referenced by place_device_in_d3hot().
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inlinestatic |
Definition at line 48 of file southcluster.c.
References base, LPC_DEFAULT_IO_RANGE_LOWER, and LPC_DEFAULT_IO_RANGE_UPPER.
Referenced by sc_add_io_resource().
int __weak mainboard_get_spi_config | ( | struct spi_config * | cfg | ) |
Definition at line 498 of file southcluster.c.
Referenced by finalize_chipset().
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static |
Definition at line 329 of file southcluster.c.
References pci_path::devfn, EHCI_DEV, EHCI_FUNC, HDA_DEV, HDA_FUNC, hda_work_around(), HSUART1_DEV, HSUART1_FUNC, HSUART2_DEV, HSUART2_FUNC, I2C1_DEV, I2C1_FUNC, I2C2_DEV, I2C2_FUNC, I2C3_DEV, I2C3_FUNC, I2C4_DEV, I2C4_FUNC, I2C5_DEV, I2C5_FUNC, I2C6_DEV, I2C6_FUNC, I2C7_DEV, I2C7_FUNC, LPE_DEV, LPE_FUNC, MMC45_DEV, MMC45_FUNC, MMC_DEV, MMC_FUNC, offset, device::path, device_path::pci, PCI_CAP_ID_PM, PCI_DEVFN, pci_find_capability(), PCIE_PORT1_DEV, PCIE_PORT1_FUNC, PCIE_PORT2_DEV, PCIE_PORT2_FUNC, PCIE_PORT3_DEV, PCIE_PORT3_FUNC, PCIE_PORT4_DEV, PCIE_PORT4_FUNC, PWM1_DEV, PWM1_FUNC, PWM2_DEV, PWM2_FUNC, SATA_DEV, SATA_FUNC, SD_DEV, SD_FUNC, SDIO_DEV, SDIO_FUNC, set_d3hot_bits(), SIO_DMA1_DEV, SIO_DMA1_FUNC, SIO_DMA2_DEV, SIO_DMA2_FUNC, SMBUS_DEV, SMBUS_FUNC, SPI_DEV, SPI_FUNC, TXE_DEV, TXE_FUNC, XHCI_DEV, and XHCI_FUNC.
Definition at line 66 of file southcluster.c.
References resource::base, base, resource::flags, resource::index, io_range_in_default(), IORESOURCE_ASSIGNED, IORESOURCE_FIXED, IORESOURCE_IO, new_resource(), and resource::size.
Referenced by sc_add_io_resources().
Definition at line 79 of file southcluster.c.
References ABASE, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, resource::base, resource::flags, GBASE, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, IORESOURCE_ASSIGNED, IORESOURCE_FIXED, IORESOURCE_IO, LPC_DEFAULT_IO_RANGE_LOWER, LPC_DEFAULT_IO_RANGE_UPPER, new_resource(), sc_add_io_resource(), and resource::size.
Referenced by sc_read_resources().
Definition at line 32 of file southcluster.c.
References ABORT_BASE_ADDRESS, ABORT_BASE_SIZE, add_mmio_resource(), IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE, IO_BASE_ADDRESS, IO_BASE_SIZE, IOBASE, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE, SBASE, SPI_BASE_ADDRESS, and SPI_BASE_SIZE.
Referenced by sc_read_resources().
Definition at line 185 of file southcluster.c.
References pci_path::devfn, EHCI_DEV, EHCI_DIS, EHCI_FUNC, FUNC_DIS, FUNC_DIS2, HDA_DEV, HDA_DIS, HDA_FUNC, HSUART1_DEV, HSUART1_DIS, HSUART1_FUNC, HSUART2_DEV, HSUART2_DIS, HSUART2_FUNC, I2C1_DEV, I2C1_DIS, I2C1_FUNC, I2C2_DEV, I2C2_FUNC, I2C3_DEV, I2C3_DIS, I2C3_FUNC, I2C4_DEV, I2C4_DIS, I2C4_FUNC, I2C5_DEV, I2C5_DIS, I2C5_FUNC, I2C6_DEV, I2C6_DIS, I2C6_FUNC, I2C7_DEV, I2C7_DIS, I2C7_FUNC, LPE_DEV, LPE_DIS, LPE_FUNC, mask, MMC45_DEV, MMC45_DIS, MMC45_FUNC, MMC_DEV, MMC_DIS, MMC_FUNC, device::path, device_path::pci, PCI_DEVFN, PCIE_PORT1_DEV, PCIE_PORT1_DIS, PCIE_PORT1_FUNC, PCIE_PORT2_DEV, PCIE_PORT2_DIS, PCIE_PORT2_FUNC, PCIE_PORT3_DEV, PCIE_PORT3_DIS, PCIE_PORT3_FUNC, PCIE_PORT4_DEV, PCIE_PORT4_DIS, PCIE_PORT4_FUNC, PMC_BASE_ADDRESS, PWM1_DEV, PWM1_DIS, PWM1_FUNC, PWM2_DEV, PWM2_DIS, PWM2_FUNC, read32(), SATA_DEV, SATA_DIS, SATA_FUNC, SD_DEV, SD_DIS, SD_FUNC, SDIO_DEV, SDIO_DIS, SDIO_FUNC, SIO_DMA1_DEV, SIO_DMA1_DIS, SIO_DMA1_FUNC, SIO_DMA2_DEV, SIO_DMA2_DIS, SIO_DMA2_FUNC, SMBUS_DEV, SMBUS_DIS, SMBUS_FUNC, SPI_DEV, SPI_DIS, SPI_FUNC, TXE_DEV, TXE_DIS, TXE_FUNC, USH_SS_PHY_DIS, write32(), XHCI_DEV, XHCI_DIS, and XHCI_FUNC.
Definition at line 144 of file southcluster.c.
References acpi_is_wakeup_s3(), ACTL, BIOS_DEBUG, cmos_init(), com1_configure_resume(), config, config_of(), DIS_SLP_X_STRCH_SUS_UP, GEN_PMCON1, global_baytrail_irq_route, ILB_BASE_ADDRESS, NUM_IR_DEVS, NUM_PIRQS, baytrail_irq_route::pcidev, baytrail_irq_route::pic, PMC_BASE_ADDRESS, printk, read32(), rtc_failure(), SCIS_IRQ9, SCIS_MASK, write16(), write32(), and write8().
Definition at line 96 of file southcluster.c.
References pci_dev_read_resources(), sc_add_io_resources(), and sc_add_mmio_resources().
Definition at line 297 of file southcluster.c.
References BIOS_DEBUG, offset, pci_read_config8(), pci_write_config8(), and printk.
Referenced by place_device_in_d3hot().
Definition at line 452 of file southcluster.c.
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Definition at line 452 of file southcluster.c.
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Definition at line 452 of file southcluster.c.