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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <option.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
#include <acpi/acpigen.h>
#include <cpu/x86/smm.h>
#include <string.h>
#include "chip.h"
#include "pch.h"
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/rcba_pirq.h>
#include <southbridge/intel/common/rtc.h>
#include <southbridge/intel/common/spi.h>
#include <types.h>
Go to the source code of this file.
Macros | |
#define | NMI_OFF 0 |
Typedefs | |
typedef struct southbridge_intel_bd82x6x_config | config_t |
Functions | |
static void | pch_enable_ioapic (struct device *dev) |
Set miscellaneous static southbridge features. More... | |
static void | pch_enable_serial_irqs (struct device *dev) |
static void | pch_pirq_init (struct device *dev) |
static void | pch_gpi_routing (struct device *dev) |
static void | pch_power_options (struct device *dev) |
static void | cpt_pm_init (struct device *dev) |
static void | ppt_pm_init (struct device *dev) |
static void | enable_hpet (struct device *const dev) |
static void | enable_clock_gating (struct device *dev) |
static void | pch_set_acpi_mode (void) |
static void | pch_fixups (struct device *dev) |
static void | pch_spi_init (const struct device *const dev) |
static void | report_pch_info (struct device *dev) |
static void | lpc_init (struct device *dev) |
static void | pch_lpc_read_resources (struct device *dev) |
static void | pch_lpc_enable (struct device *dev) |
static const char * | lpc_acpi_name (const struct device *dev) |
static void | southbridge_fill_ssdt (const struct device *device) |
static void | lpc_final (struct device *dev) |
void | intel_southbridge_override_spi (struct intel_swseq_spi_config *spi_config) |
Variables | |
struct { | |
u16 dev_id | |
const char * dev_name | |
} | pch_table [] |
static struct device_operations | device_ops |
static const unsigned short | pci_device_ids [] |
static const struct pci_driver pch_lpc | __pci_driver |
typedef struct southbridge_intel_bd82x6x_config config_t |
Definition at line 248 of file lpc.c.
References BIOS_DEBUG, CIR10, CIR11, CIR12, CIR13, CIR14, CIR15, CIR16, CIR17, CIR18, CIR19, CIR2, CIR20, CIR21, CIR22, CIR23, CIR24, CIR25, CIR26, CIR27, CIR28, CIR29, CIR3, CIR30, CIR5, CIR6, CIR7, CIR8, CIR9, DMC, pci_write_config8(), PM_CFG, PMSYNC_CFG, printk, RCBA16_AND_OR, RCBA32, and RCBA32_AND_OR.
Referenced by lpc_init().
Definition at line 349 of file lpc.c.
References CG, DMIC, GEN_PMCON_1, get_platform_type(), pch_iobp_update(), pci_read_config16(), pci_write_config16(), PLATFORM_DESKTOP_SERVER, PLATFORM_MOBILE, RCBA32, RCBA32_AND_OR, and RCBA32_OR.
Referenced by lpc_init().
Definition at line 332 of file lpc.c.
References HPTC, LPC_HnBDF, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, pci_write_config16(), and RCBA32.
Referenced by lpc_init().
void intel_southbridge_override_spi | ( | struct intel_swseq_spi_config * | spi_config | ) |
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Definition at line 634 of file lpc.c.
References acpi_is_wakeup_s3(), APM_CNT_FINALIZE, apm_control(), CONFIG, and spi_finalize_ops().
Definition at line 492 of file lpc.c.
References BIOS_DEBUG, BIOS_ERR, cpt_pm_init(), device::device, enable_clock_gating(), enable_hpet(), i8259_configure_irq_trigger(), isa_dma_init(), pch_enable_ioapic(), pch_enable_serial_irqs(), pch_fixups(), pch_pirq_init(), pch_power_options(), pch_set_acpi_mode(), pch_silicon_type(), pch_spi_init(), PCH_TYPE_CPT, PCH_TYPE_PPT, ppt_pm_init(), printk, report_pch_info(), sb_rtc_init(), and setup_i8259().
Set miscellaneous static southbridge features.
dev | PCI device with I/O APIC control registers |
Definition at line 38 of file lpc.c.
References ioapic_lock_max_vectors(), LPC_IBDF, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, pci_write_config16(), setup_ioapic(), and VIO_APIC_VADDR.
Referenced by lpc_init().
Definition at line 50 of file lpc.c.
References pci_write_config8(), and SERIRQ_CNTL.
Referenced by lpc_init().
Definition at line 397 of file lpc.c.
References DMC, GEN_PMCON_2, LCAP, LCTL, pci_or_config8(), RCBA32_AND_OR, and RCBA32_OR.
Referenced by lpc_init().
Definition at line 119 of file lpc.c.
References device::chip_info, config, GPIO_ROUT, and pci_write_config32().
Referenced by pch_power_options().
Definition at line 611 of file lpc.c.
References DISPBDF, FD2, pch_enable(), PCH_ENABLE_DBDF, RCBA16, and RCBA32_OR.
Definition at line 547 of file lpc.c.
References resource::base, device::chip_info, config, resource::flags, IO_APIC_ADDR, IOINDEX_SUBTRACTIVE, IORESOURCE_ASSIGNED, IORESOURCE_FIXED, IORESOURCE_IO, IORESOURCE_MEM, IORESOURCE_SUBTRACTIVE, new_resource(), pci_dev_read_resources(), and resource::size.
Definition at line 82 of file lpc.c.
References all_devices, DEVICE_PATH_PCI, device::enabled, device::next, device::path, PCI_INTERRUPT_LINE, PCI_INTERRUPT_PIN, pci_read_config8(), pci_write_config8(), PIRQA_ROUT, PIRQB_ROUT, PIRQC_ROUT, PIRQD_ROUT, PIRQE_ROUT, PIRQF_ROUT, PIRQG_ROUT, PIRQH_ROUT, and device_path::type.
Referenced by lpc_init().
Definition at line 148 of file lpc.c.
References ALT_GP_SMI_EN, BIOS_INFO, device::chip_info, config, CONFIG, GEN_PMCON_1, GEN_PMCON_3, get_uint_option(), GPE0_EN, inb(), inl(), MAINBOARD_POWER_KEEP, MAINBOARD_POWER_OFF, MAINBOARD_POWER_ON, NMI_OFF, outb(), outl(), outw(), pch_gpi_routing(), pci_read_config16(), pci_write_config16(), pmbase, printk, PRSTS, and RCBA32.
Referenced by lpc_init().
Definition at line 390 of file lpc.c.
References acpi_is_wakeup_s3(), APM_CNT_ACPI_DISABLE, and apm_control().
Referenced by lpc_init().
Definition at line 410 of file lpc.c.
References BIOS_DEBUG, device::chip_info, config, printk, RCBA32, and RCBA32_OR.
Referenced by lpc_init().
Definition at line 290 of file lpc.c.
References BIOS_DEBUG, CIR10, CIR11, CIR12, CIR13, CIR14, CIR15, CIR16, CIR17, CIR18, CIR19, CIR2, CIR20, CIR21, CIR22, CIR23, CIR24, CIR25, CIR26, CIR27, CIR28, CIR29, CIR3, CIR30, CIR5, CIR6, CIR7, CIR8, CIR9, DMC, pci_write_config8(), PM_CFG, PMSYNC_CFG, printk, RCBA16_AND_OR, RCBA32, and RCBA32_AND_OR.
Referenced by lpc_init().
Definition at line 476 of file lpc.c.
References ARRAY_SIZE, BIOS_INFO, dev_id, pch_table, pch_type(), PCI_CLASS_REVISION, PCI_DEVICE_ID, pci_read_config16(), pci_read_config8(), and printk.
Referenced by lpc_init().
Definition at line 625 of file lpc.c.
References chip, device::chip_info, intel_acpi_gen_def_acpi_pirq(), intel_acpi_pcie_hotplug_generator(), and pcidev_on_root().
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u16 dev_id |
Definition at line 426 of file lpc.c.
Referenced by report_pch_info().
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const { ... } pch_table[] |
Referenced by report_pch_info().
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