12 #include <soc/pci_devs.h>
13 #include <soc/romstage.h>
14 #include <soc/systemagent.h>
79 char cpu_string[50], *cpu_name = cpu_string;
81 const char *mode[] = {
"NOT ",
""};
85 cpuidr =
cpuid(index);
86 if (cpuidr.
eax < 0x80000004) {
87 strcpy(cpu_string,
"Platform info not available");
89 u32 *p = (
u32 *)cpu_string;
90 for (i = 2; i <= 4 ; i++) {
91 cpuidr =
cpuid(index + i);
99 while (cpu_name[0] ==
' ')
117 aes = (cpu_feature_flag &
CPUID_AES) ? 1 : 0;
118 txt = (cpu_feature_flag &
CPUID_SMX) ? 1 : 0;
119 vt = (cpu_feature_flag &
CPUID_VMX) ? 1 : 0;
121 "VT %ssupported\n", mode[aes], mode[txt], mode[vt]);
129 const char *mch_type =
"Unknown";
142 mch_device, mch_revision, mch_type);
165 const char *igd_type =
"Unknown";
#define MCH_BROADWELL_ID_U_Y
#define IGD_BROADWELL_Y_GT2
#define IGD_BROADWELL_H_GT2
#define IGD_HASWELL_ULT_GT3
#define IGD_HASWELL_ULT_GT1
#define IGD_BROADWELL_U_GT3_15W
#define MCH_BROADWELL_REV_F0
#define IGD_BROADWELL_H_GT3
#define IGD_HASWELL_ULT_GT2
#define IGD_BROADWELL_U_GT1
#define IGD_BROADWELL_U_GT3_28W
#define IGD_BROADWELL_U_GT2
#define MCH_BROADWELL_REV_E0
#define MCH_BROADWELL_REV_D0
#define printk(level,...)
#define CPUID_BROADWELL_ULT_C0
#define CPUID_HASWELL_ULT_C0
#define CPUID_HASWELL_ULT_B0
#define CPUID_CRYSTALWELL_C0
#define CPUID_BROADWELL_ULT_E0
#define CPUID_BROADWELL_ULT_D0
uint32_t cpu_get_feature_flags_ecx(void)
uint32_t cpu_get_cpuid(void)
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
uint32_t get_current_microcode_rev(void)
#define PCH_LPT_LP_SAMPLE
#define PCH_WPT_BDW_Y_SAMPLE
#define PCH_LPT_LP_MAINSTREAM
#define PCH_WPT_BDW_U_SAMPLE
#define PCH_WPT_HSW_U_SAMPLE
#define PCH_WPT_BDW_Y_BASE
#define PCH_LPT_LP_PREMIUM
#define PCH_WPT_BDW_Y_PREMIUM
#define PCH_WPT_BDW_U_BASE
#define PCH_WPT_BDW_U_PREMIUM
char * strcpy(char *dst, const char *src)