25 #define MAX_NODE_NUMS MAX_NODES
41 tempreg = (
nodeid&0xf) | ((
nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4));
44 tempreg = 3 | ((io_min&0xf0)<<(12-4));
54 tempreg = (
nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00);
55 for (i = 0; i < nodes; i++)
57 tempreg = 3 | (
nodeid & 0x30) | (mmio_min&0xffffff00);
79 die(
"Cannot find 0:0x18.[0|1]\n");
120 *basek = ((temp & 0xffff0000)) >> (10 - 8);
126 *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8);
157 unsigned int goal_nodeid,
unsigned int goal_link)
160 unsigned int nodeid, link = 0;
168 for (link = 0; !res && (link < 8); link++) {
175 if ((goal_link == (link - 1)) &&
176 (goal_nodeid == (
nodeid - 1)) &&
185 unsigned int nodeid,
unsigned int link)
191 for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
218 for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
359 #if CONFIG(MULTIPLE_VGA_ADAPTERS)
404 void *
addr, *current;
407 current = (
void *)(hest + 1);
419 return (
unsigned long)current;
425 char pscope[] =
"\\_SB.PCI0";
450 if (*(
uint32_t *)((
unsigned long)ssdt + i) == 0x5f52505f)
451 *(
uint32_t *)((
unsigned long)ssdt + i) = 0x5f42535f;
459 unsigned long current,
470 current =
ALIGN(current, 8);
476 current =
ALIGN(current, 8);
489 current =
ALIGN(current, 8);
502 current =
ALIGN(current, 8);
515 current =
ALIGN(current, 16);
530 current =
ALIGN(current, 16);
557 static const struct pci_driver family16_northbridge
__pci_driver = {
563 static const struct pci_driver family10_northbridge
__pci_driver = {
598 for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
603 if ((
base & 3) != 0) {
604 unsigned int nodeid, reg_link;
611 reg_link = (limit >> 4) & 7;
629 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
630 struct hw_mem_hole_info {
631 unsigned int hole_startk;
634 static struct hw_mem_hole_info get_hw_mem_hole_info(
void)
636 struct hw_mem_hole_info mem_hole;
638 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
639 mem_hole.node_id = -1;
647 mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
648 mem_hole.node_id = i;
656 if (mem_hole.node_id == -1) {
662 if (base_k > 4 *1024 * 1024)
break;
663 if (limitk_pri != base_k) {
664 mem_hole.hole_startk = (
unsigned int)limitk_pri;
665 mem_hole.node_id = i;
668 limitk_pri = limit_k;
677 unsigned long mmio_basek;
681 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
682 struct hw_mem_hole_info mem_hole;
685 pci_tolm = 0xffffffffUL;
692 mmio_basek = pci_tolm >> 10;
694 mmio_basek &= ~((1 << 6) -1);
699 mmio_basek &= ~((64*1024) - 1);
701 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
708 mem_hole = get_hw_mem_hole_info();
711 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk))
712 mmio_basek = mem_hole.hole_startk;
722 sizek = limitk - basek;
725 if (basek < 640 && sizek > 768) {
729 sizek = limitk - basek;
735 if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
736 if (basek <= mmio_basek) {
737 unsigned int pre_sizek;
738 pre_sizek = mmio_basek - basek;
746 if ((basek + sizek) <= 4*1024*1024) {
752 sizek = topmem2/1024 - basek;
758 printk(
BIOS_DEBUG,
"node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
759 i, mmio_basek, basek, limitk);
799 unsigned int ApicIdCoreIdSize;
800 unsigned int core_nums;
812 coreid_bits = (
cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
813 core_max = 1 << (coreid_bits & 0x000F);
815 ApicIdCoreIdSize = ((
cpuid_ecx(0x80000008)>>12) & 0xF);
816 if (ApicIdCoreIdSize) {
817 core_nums = (1 << ApicIdCoreIdSize) - 1;
839 for (fn = 0; fn <= 5; fn++) {
852 family = (family >> 20) & 0xFF;
857 siblings = ((dword &
BIT15) >> 13) | ((dword & (
BIT13 |
BIT12)) >> 12);
858 }
else if (family == 7) {
860 if (cdb_dev && cdb_dev->
enabled) {
867 int enable_node = cdb_dev && cdb_dev->
enabled;
868 printk(
BIOS_SPEW,
"%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
869 dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
871 for (j = 0; j <= siblings; j++) {
872 extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
873 u32 modules = TopologyConfiguration.PlatformNumberOfModules;
874 u32 lapicid_start = 0;
890 u8 plat_num_io_apics = 3;
892 if ((
node_nums * core_max) + plat_num_io_apics >= 0x10) {
893 lapicid_start = (plat_num_io_apics - 1) / core_max;
894 lapicid_start = (lapicid_start + 1) * core_max;
897 u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
940 u32 new_vendev = vendev;
955 new_vendev = 0x10029830;
961 if (vendev != new_vendev)
void acpi_add_table(acpi_rsdp_t *rsdp, void *table)
Add an ACPI table to the RSDT (and XSDT) structure, recalculate length and checksum.
u8 acpi_checksum(u8 *table, u32 length)
unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 data_len)
void acpi_write_hest(acpi_hest_t *hest, unsigned long(*acpi_fill_hest)(acpi_hest_t *hest))
void acpigen_pop_len(void)
void acpigen_write_scope(const char *name)
void acpigen_write_name_dword(const char *name, uint32_t val)
static uint64_t amd_topmem2(void)
void add_uma_resource_below_tolm(struct device *nb, int idx)
static unsigned int cpuid_ecx(unsigned int op)
static unsigned int cpuid_eax(unsigned int op)
void * memcpy(void *dest, const void *src, size_t n)
#define printk(level,...)
void __noreturn die(const char *fmt,...)
static __always_inline unsigned long nodeid(void)
struct device * add_cpu_device(struct bus *cpu_bus, unsigned int apic_id, int enabled)
void assign_resources(struct bus *bus)
Assign the computed resources to the devices on the bus.
DEVTREE_CONST struct device * pcidev_on_root(uint8_t dev, uint8_t fn)
struct resource * new_resource(struct device *dev, unsigned int index)
See if a resource structure already exists for a given index and if not allocate one.
void mmconf_resource(struct device *dev, unsigned long index)
struct resource * probe_resource(const struct device *dev, unsigned int index)
See if a resource structure already exists for a given index.
u32 find_pci_tolm(struct bus *bus)
void report_resource_stored(struct device *dev, const struct resource *resource, const char *comment)
Print the resource that was just stored.
resource_t resource_end(const struct resource *resource)
Compute the maximum address that is part of a resource.
const char * dev_path(const struct device *dev)
void add_more_links(struct device *dev, unsigned int total_links)
Ensure the device has a minimum number of bus links.
void * agesawrapper_getlateinitptr(int pick)
struct acpi_table_header acpi_header_t
static __always_inline msr_t rdmsr(unsigned int index)
static void noop_read_resources(struct device *dev)
Standard device operations function pointers shims.
static void noop_set_resources(struct device *dev)
#define ram_resource(dev, idx, basek, sizek)
#define amd_cpu_topology(cpu, node, core)
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
void initialize_cpus(struct bus *cpu_bus)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define BIOS_NOTICE
BIOS_NOTICE - Unexpected but relatively insignificant.
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
#define BIOS_SPEW
BIOS_SPEW - Excessively verbose output.
#define HT_MEM_HOST_ALIGN
u32 map_oprom_vendev(u32 vendev)
static void sysconf_init(struct device *dev)
static u32 amdfam16_nodeid(struct device *dev)
static void cpu_bus_init(struct device *dev)
static void get_fx_devs(void)
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
static struct device * __f1_dev[MAX_NODE_NUMS]
static const struct pci_driver family16_northbridge __pci_driver
static struct device_operations cpu_bus_ops
static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, unsigned int goal_link)
static struct device * __f0_dev[MAX_NODE_NUMS]
static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk)
static struct device_operations pci_domain_ops
static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max)
static void root_complex_enable_dev(struct device *dev)
static void set_resources(struct device *dev)
static void f1_write_config32(unsigned int reg, u32 value)
static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
static void create_vga_resource(struct device *dev, unsigned int nodeid)
I tried to reuse the resource allocation code in set_resource() but it is too difficult to deal with ...
static void northbridge_fill_ssdt_generator(const struct device *device)
static struct device * __f2_dev[MAX_NODE_NUMS]
static struct resource * amdfam16_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link)
static unsigned int sblink
static void cpu_bus_scan(struct device *dev)
struct chip_operations northbridge_amd_agesa_family16kb_ops
struct chip_operations northbridge_amd_agesa_family16kb_root_complex_ops
static unsigned int fx_devs
static unsigned int node_nums
static void fam16_finalize(void *chip_info)
static struct device_operations northbridge_operations
static void read_resources(struct device *dev)
static struct device * __f4_dev[MAX_NODE_NUMS]
static void set_vga_enable_reg(u32 nodeid, u32 linkn)
static struct device * get_node_pci(u32 nodeid, u32 fn)
static void domain_set_resources(struct device *dev)
static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
static const char * domain_acpi_name(const struct device *dev)
static unsigned long acpi_fill_hest(acpi_hest_t *hest)
static void domain_read_resources(struct device *dev)
static u32 f1_read_config32(unsigned int reg)
static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
static struct resource * amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link)
static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link)
@ DEVICE_PATH_CPU_CLUSTER
#define PCI_DEVFN(slot, func)
#define PCI_BRIDGE_CTL_VGA
struct device * pci_probe_dev(struct device *dev, struct bus *bus, unsigned int devfn)
Scan a PCI bus.
void pci_domain_read_resources(struct device *dev)
void pci_dev_enable_resources(struct device *dev)
void pci_domain_scan_bus(struct device *dev)
Scan a PCI domain.
#define PCI_DID_AMD_16H_MODEL_000F_NB_HT
#define PCI_DID_AMD_10H_NB_HT
#define IOINDEX(IDX, LINK)
#define IORESOURCE_STORED
#define IORESOURCE_ASSIGNED
#define IOINDEX_LINK(IDX)
#define IORESOURCE_PREFETCH
#define IORESOURCE_BRIDGE
unsigned long long uint64_t
DEVTREE_CONST struct bus * next
DEVTREE_CONST struct device * children
DEVTREE_CONST struct device * dev
void(* read_resources)(struct device *dev)
enum device_path_type type
struct device_operations * ops
DEVTREE_CONST struct bus * bus
DEVTREE_CONST struct bus * link_list
DEVTREE_CONST struct resource * resource_list
DEVTREE_CONST struct resource * next
int snprintf(char *buf, size_t size, const char *fmt,...)
Note: This file is only for POSIX compatibility, and is meant to be chain-included via string....
typedef void(X86APIP X86EMU_intrFuncs)(int num)